Skip to content

Commit 01cc246

Browse files
MaskRayMaskRay
committed
ELF: Synthesize R_RISCV_ALIGN at input section start
See also https://sourceware.org/bugzilla/show_bug.cgi?id=33236
1 parent 1acfa18 commit 01cc246

File tree

6 files changed

+255
-4
lines changed

6 files changed

+255
-4
lines changed

‎lld/ELF/Arch/RISCV.cpp

Lines changed: 106 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -45,7 +45,17 @@ class RISCV final : public TargetInfo {
4545
uint64_t val) const override;
4646
void relocateAlloc(InputSectionBase &sec, uint8_t *buf) const override;
4747
bool relaxOnce(int pass) const override;
48+
template <class ELFT, class RelTy>
49+
bool synthesizeAlignOne(uint64_t &dot, InputSection *sec, Relocs<RelTy> rels);
50+
template <class ELFT, class RelTy>
51+
void synthesizeAlignEnd(uint64_t &dot, InputSection *sec, Relocs<RelTy> rels);
52+
template <class ELFT>
53+
bool synthesizeAlignAux(uint64_t &dot, InputSection *sec);
54+
bool maybeSynthesizeAlign(uint64_t &dot, InputSection *sec) override;
4855
void finalizeRelax(int passes) const override;
56+
57+
InputSection *baseSec = nullptr;
58+
SmallVector<std::pair<uint64_t, uint64_t>, 0> synthesizedAligns;
4959
};
5060

5161
} // end anonymous namespace
@@ -959,10 +969,106 @@ bool RISCV::relaxOnce(int pass) const {
959969
return changed;
960970
}
961971

972+
template <class ELFT, class RelTy>
973+
bool RISCV::synthesizeAlignOne(uint64_t &dot, InputSection *sec,
974+
Relocs<RelTy> rels) {
975+
if (!baseSec) {
976+
// Record the first section with RELAX relocations.
977+
for (auto rel : rels) {
978+
if (rel.getType(false) == R_RISCV_RELAX) {
979+
baseSec = sec;
980+
break;
981+
}
982+
}
983+
} else if (sec->addralign >= 4) {
984+
// If the alignment is >= 4 and the section does not start with an ALIGN
985+
// relocation, synthesize one.
986+
bool alignRel = false;
987+
for (auto rel : rels) {
988+
if (rel.r_offset == 0 && rel.getType(false) == R_RISCV_ALIGN)
989+
alignRel = true;
990+
break;
991+
}
992+
if (!alignRel) {
993+
synthesizedAligns.emplace_back(dot - baseSec->getVA(),
994+
sec->addralign - 2);
995+
dot += sec->addralign - 2;
996+
return true;
997+
}
998+
}
999+
return false;
1000+
}
1001+
1002+
template <class ELFT, class RelTy>
1003+
void RISCV::synthesizeAlignEnd(uint64_t &dot, InputSection *sec,
1004+
Relocs<RelTy> rels) {
1005+
auto *f = cast<ObjFile<ELFT>>(baseSec->file);
1006+
auto shdr = f->template getELFShdrs<ELFT>()[baseSec->relSecIdx];
1007+
sec = make<InputSection>(*f, shdr, baseSec->name);
1008+
auto *baseRelSec = cast<InputSection>(f->getSections()[baseSec->relSecIdx]);
1009+
baseSec = nullptr;
1010+
*sec = *baseRelSec;
1011+
1012+
auto newSize = rels.size() + synthesizedAligns.size();
1013+
auto *relas = makeThreadLocalN<typename ELFT::Rela>(newSize);
1014+
sec->size = newSize * sizeof(typename ELFT::Rela);
1015+
sec->content_ = reinterpret_cast<uint8_t *>(relas);
1016+
sec->type = SHT_RELA;
1017+
// Copy original relocations.
1018+
for (auto [i, r] : llvm::enumerate(rels)) {
1019+
relas[i].r_offset = r.r_offset;
1020+
relas[i].setSymbolAndType(r.getSymbol(0), r.getType(0), false);
1021+
relas[i].r_addend = r.r_addend;
1022+
}
1023+
// Append synthesized ALIGN relocations.
1024+
for (auto [i, r] : llvm::enumerate(synthesizedAligns)) {
1025+
auto &rela = relas[rels.size() + i];
1026+
rela.r_offset = r.first;
1027+
rela.setSymbolAndType(0, R_RISCV_ALIGN, false);
1028+
rela.r_addend = r.second;
1029+
}
1030+
// In the output relocation section, replace the old relocation section with
1031+
// the new one.
1032+
for (SectionCommand *cmd : sec->getParent()->commands) {
1033+
auto *isd = dyn_cast<InputSectionDescription>(cmd);
1034+
if (!isd)
1035+
continue;
1036+
for (auto *&isec : isd->sections)
1037+
if (isec == baseRelSec)
1038+
isec = sec;
1039+
}
1040+
}
1041+
1042+
template <class ELFT>
1043+
bool RISCV::synthesizeAlignAux(uint64_t &dot, InputSection *sec) {
1044+
bool ret = false;
1045+
if (sec) {
1046+
invokeOnRelocs(*sec, ret = synthesizeAlignOne<ELFT>, dot, sec);
1047+
} else if (baseSec) {
1048+
invokeOnRelocs(*baseSec, synthesizeAlignEnd<ELFT>, dot, sec);
1049+
}
1050+
return ret;
1051+
}
1052+
1053+
// When called with an input section (`sec` is not null): If the section
1054+
// alignment is >= 4, advance `dot` to insert NOPs and synthesize an ALIGN
1055+
// relocation.
1056+
//
1057+
// When called after all input sections are processed (`sec` is null): The
1058+
// output relocation section is updated with all the newly synthesized ALIGN
1059+
// relocations.
1060+
bool RISCV::maybeSynthesizeAlign(uint64_t &dot, InputSection *sec) {
1061+
assert(ctx.arg.relocatable);
1062+
if (ctx.arg.is64)
1063+
return synthesizeAlignAux<ELF64LE>(dot, sec);
1064+
return synthesizeAlignAux<ELF32LE>(dot, sec);
1065+
}
1066+
9621067
void RISCV::finalizeRelax(int passes) const {
9631068
llvm::TimeTraceScope timeScope("Finalize RISC-V relaxation");
9641069
Log(ctx) << "relaxation passes: " << passes;
9651070
SmallVector<InputSection *, 0> storage;
1071+
9661072
for (OutputSection *osec : ctx.outputSections) {
9671073
if (!(osec->flags & SHF_EXECINSTR))
9681074
continue;

‎lld/ELF/LinkerScript.cpp

Lines changed: 11 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1230,6 +1230,9 @@ bool LinkerScript::assignOffsets(OutputSection *sec) {
12301230
if (sec->firstInOverlay)
12311231
state->overlaySize = 0;
12321232

1233+
bool synthesizeAlign =
1234+
(sec->flags & SHF_EXECINSTR) && ctx.arg.relocatable && ctx.arg.relax &&
1235+
is_contained({EM_RISCV, EM_LOONGARCH}, ctx.arg.emachine);
12331236
// We visited SectionsCommands from processSectionCommands to
12341237
// layout sections. Now, we visit SectionsCommands again to fix
12351238
// section offsets.
@@ -1260,7 +1263,8 @@ bool LinkerScript::assignOffsets(OutputSection *sec) {
12601263
if (isa<PotentialSpillSection>(isec))
12611264
continue;
12621265
const uint64_t pos = dot;
1263-
dot = alignToPowerOf2(dot, isec->addralign);
1266+
if (!(synthesizeAlign && ctx.target->maybeSynthesizeAlign(dot, isec)))
1267+
dot = alignToPowerOf2(dot, isec->addralign);
12641268
isec->outSecOff = dot - sec->addr;
12651269
dot += isec->getSize();
12661270

@@ -1276,6 +1280,12 @@ bool LinkerScript::assignOffsets(OutputSection *sec) {
12761280
if (ctx.in.relroPadding && sec == ctx.in.relroPadding->getParent())
12771281
expandOutputSection(alignToPowerOf2(dot, ctx.arg.commonPageSize) - dot);
12781282

1283+
if (synthesizeAlign) {
1284+
const uint64_t pos = dot;
1285+
ctx.target->maybeSynthesizeAlign(dot, nullptr);
1286+
expandOutputSection(dot - pos);
1287+
}
1288+
12791289
// Non-SHF_ALLOC sections do not affect the addresses of other OutputSections
12801290
// as they are not part of the process image.
12811291
if (!(sec->flags & SHF_ALLOC)) {

‎lld/ELF/OutputSections.cpp

Lines changed: 8 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -889,9 +889,14 @@ void OutputSection::sortInitFini() {
889889
std::array<uint8_t, 4> OutputSection::getFiller(Ctx &ctx) {
890890
if (filler)
891891
return *filler;
892-
if (flags & SHF_EXECINSTR)
893-
return ctx.target->trapInstr;
894-
return {0, 0, 0, 0};
892+
if (!(flags & SHF_EXECINSTR))
893+
return {0, 0, 0, 0};
894+
if (ctx.arg.relocatable && ctx.arg.emachine == EM_RISCV) {
895+
if (ctx.arg.eflags & EF_RISCV_RVC)
896+
return {1, 0, 1, 0};
897+
return {0x13, 0, 0, 0};
898+
}
899+
return ctx.target->trapInstr;
895900
}
896901

897902
void OutputSection::checkDynRelAddends(Ctx &ctx) {

‎lld/ELF/Target.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -96,6 +96,9 @@ class TargetInfo {
9696

9797
// Do a linker relaxation pass and return true if we changed something.
9898
virtual bool relaxOnce(int pass) const { return false; }
99+
virtual bool maybeSynthesizeAlign(uint64_t &dot, InputSection *sec) {
100+
return false;
101+
}
99102
// Do finalize relaxation after collecting relaxation infos.
100103
virtual void finalizeRelax(int passes) const {}
101104

‎lld/ELF/Writer.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1543,6 +1543,8 @@ template <class ELFT> void Writer<ELFT>::finalizeAddressDependentContent() {
15431543

15441544
uint32_t pass = 0, assignPasses = 0;
15451545
for (;;) {
1546+
if (ctx.arg.relocatable)
1547+
break;
15461548
bool changed = ctx.target->needsThunks
15471549
? tc.createThunks(pass, ctx.outputSections)
15481550
: ctx.target->relaxOnce(pass);

‎lld/test/ELF/riscv-relocatable-align.s

Lines changed: 125 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,125 @@
1+
# RUN: rm -rf %t && split-file %s %t && cd %t
2+
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+c,+relax a.s -o ac.o
3+
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+c,+relax b.s -o bc.o
4+
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+c,+relax b1.s -o b1c.o
5+
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+c,+relax c.s -o cc.o
6+
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+c,+relax d.s -o dc.o
7+
# RUN: ld.lld -r bc.o bc.o ac.o bc.o b1c.o cc.o dc.o -o out.ro
8+
# RUN: llvm-objdump -dr -M no-aliases out.ro | FileCheck %s
9+
10+
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+relax a.s -o a.o
11+
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+relax b.s -o b.o
12+
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+relax d.s -o d.o
13+
# RUN: ld.lld -r a.o b.o d.o -o out0.ro
14+
# RUN: ld.lld -Ttext=0x10000 out0.ro -o out0
15+
# RUN: llvm-objdump -dr -M no-aliases out0 | FileCheck %s --check-prefix=CHECK1
16+
17+
# CHECK: <b0>:
18+
# CHECK-NEXT: 0: 00158513 addi a0, a1, 0x1
19+
# CHECK-NEXT: 4: 0001 c.nop
20+
# CHECK-NEXT: 6: 0001 c.nop
21+
# CHECK-EMPTY:
22+
# CHECK-NEXT: <b0>:
23+
# CHECK-NEXT: 8: 00158513 addi a0, a1, 0x1
24+
# CHECK-EMPTY:
25+
# CHECK-NEXT: <_start>:
26+
# CHECK-NEXT: c: 00000097 auipc ra, 0x0
27+
# CHECK-NEXT: 000000000000000c: R_RISCV_CALL_PLT foo
28+
# CHECK-NEXT: 000000000000000c: R_RISCV_RELAX *ABS*
29+
# CHECK-NEXT: 10: 000080e7 jalr ra, 0x0(ra) <_start>
30+
# CHECK-NEXT: 14: 0001 c.nop
31+
# CHECK-NEXT: 0000000000000014: R_RISCV_ALIGN *ABS*+0x6
32+
# CHECK-NEXT: 16: 0001 c.nop
33+
# CHECK-NEXT: 18: 0001 c.nop
34+
# CHECK-EMPTY:
35+
# CHECK-NEXT: <b0>:
36+
# CHECK-NEXT: 1a: 00158513 addi a0, a1, 0x1
37+
# CHECK-NEXT: 1e: 0001 c.nop
38+
# CHECK-NEXT: 20: 0001 c.nop
39+
# CHECK-NEXT: 0000000000000020: R_RISCV_ALIGN *ABS*+0x6
40+
# CHECK-NEXT: 22: 0001 c.nop
41+
# CHECK-NEXT: 24: 00000013 addi zero, zero, 0x0
42+
# CHECK-EMPTY:
43+
# CHECK-NEXT: <b0>:
44+
# CHECK-NEXT: 28: 00158513 addi a0, a1, 0x1
45+
# CHECK-EMPTY:
46+
# CHECK-NEXT: <c0>:
47+
# CHECK-NEXT: 2c: 00000097 auipc ra, 0x0
48+
# CHECK-NEXT: 000000000000002c: R_RISCV_CALL_PLT foo
49+
# CHECK-NEXT: 000000000000002c: R_RISCV_RELAX *ABS*
50+
# CHECK-NEXT: 30: 000080e7 jalr ra, 0x0(ra) <c0>
51+
# CHECK-NEXT: 34: 0001 c.nop
52+
# CHECK-NEXT: 0000000000000034: R_RISCV_ALIGN *ABS*+0x2
53+
# CHECK-EMPTY:
54+
# CHECK-NEXT: <d0>:
55+
# CHECK-NEXT: 36: 00258513 addi a0, a1, 0x2
56+
57+
# CHECK1: <_start>:
58+
# CHECK1-NEXT: 010000ef jal ra, 0x10010 <foo>
59+
# CHECK1-NEXT: 00000013 addi zero, zero, 0x0
60+
# CHECK1-EMPTY:
61+
# CHECK1-NEXT: <b0>:
62+
# CHECK1-NEXT: 00158513 addi a0, a1, 0x1
63+
# CHECK1-EMPTY:
64+
# CHECK1-NEXT: <d0>:
65+
# CHECK1-NEXT: 00258513 addi a0, a1, 0x2
66+
67+
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+c,+relax --crel a.s -o acrel.o
68+
# RUN: ld.lld -r acrel.o bc.o -o out1.ro
69+
# RUN: llvm-objdump -dr -M no-aliases out1.ro | FileCheck %s --check-prefix=CHECK2
70+
71+
# CHECK2: <_start>:
72+
# CHECK2-NEXT: 0: 00000097 auipc ra, 0x0
73+
# CHECK2-NEXT: 0000000000000000: R_RISCV_CALL_PLT foo
74+
# CHECK2-NEXT: 0000000000000000: R_RISCV_RELAX *ABS*
75+
# CHECK2-NEXT: 4: 000080e7 jalr ra, 0x0(ra) <_start>
76+
# CHECK2-NEXT: 8: 0001 c.nop
77+
# CHECK2-NEXT: 0000000000000008: R_RISCV_ALIGN *ABS*+0x6
78+
# CHECK2-NEXT: a: 0001 c.nop
79+
# CHECK2-NEXT: c: 0001 c.nop
80+
# CHECK2-EMPTY:
81+
# CHECK2-NEXT: <b0>:
82+
# CHECK2-NEXT: e: 00158513 addi a0, a1, 0x1
83+
84+
#--- a.s
85+
.globl _start
86+
_start:
87+
call foo
88+
89+
.section .text1,"ax"
90+
.globl foo
91+
foo:
92+
93+
#--- b.s
94+
## Needs synthesized ALIGN
95+
.option push
96+
.option norelax
97+
.balign 8
98+
b0:
99+
addi a0, a1, 1
100+
.option pop
101+
102+
#--- b1.s
103+
.option push
104+
.option norelax
105+
.reloc ., R_RISCV_ALIGN, 6
106+
addi x0, x0, 0
107+
c.nop
108+
.balign 8
109+
b0:
110+
addi a0, a1, 1
111+
.option pop
112+
113+
#--- c.s
114+
.balign 2
115+
c0:
116+
call foo
117+
118+
#--- d.s
119+
## Needs synthesized ALIGN
120+
.option push
121+
.option norelax
122+
.balign 4
123+
d0:
124+
addi a0, a1, 2
125+
.option pop

0 commit comments

Comments
 (0)