Skip to content

Commit 0e0331e

Browse files
committed
update
1 parent 04eb284 commit 0e0331e

File tree

1 file changed

+1
-6
lines changed

1 file changed

+1
-6
lines changed

README.md

Lines changed: 1 addition & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -10,12 +10,7 @@ digital circuit. Below is a circuit written in Verilog.
1010
<img src="image/circuit.png" height="100%" width="40%" align="right">
1111

1212
```Verilog
13-
module simple (
14-
input1,
15-
input2,
16-
input3,
17-
out
18-
);
13+
module simple (input1, input2, input3, out);
1914
2015
// primary inputs
2116
input input1;

0 commit comments

Comments
 (0)