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renamed: lib/parallel.Parallel -> lib/seq.Seq
1 parent be101f2 commit 1110c18

23 files changed

+275
-275
lines changed
File renamed without changes.
File renamed without changes.

tests/lib_parallel_/adder/lib_parallel_addr.py renamed to tests/lib_seq_/adder/lib_seq_addr.py

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,7 @@ def mkLed(numports=8):
2626
odata = m.OutputReg('odata', 32, initval=0)
2727
ovalid = m.OutputReg('ovalid', initval=0)
2828

29-
par = lib.Parallel(m, 'par')
29+
seq = lib.Seq(m, 'seq')
3030
pdata = idata
3131
pvalid = ivalid
3232
ndata = []
@@ -39,17 +39,17 @@ def mkLed(numports=8):
3939
ndata.append(td)
4040
nvalid.append(tv)
4141
cond = AndList(pvalid[i*2], pvalid[i*2+1])
42-
par.add( td(pdata[i*2] + pdata[i*2+1]), cond=cond )
43-
par.add( tv(cond) )
42+
seq.add( td(pdata[i*2] + pdata[i*2+1]), cond=cond )
43+
seq.add( tv(cond) )
4444
pdata = ndata
4545
pvalid = nvalid
4646
ndata = []
4747
nvalid = []
4848

49-
par.add( odata(pdata[-1]) )
50-
par.add( ovalid(pvalid[-1]) )
49+
seq.add( odata(pdata[-1]) )
50+
seq.add( ovalid(pvalid[-1]) )
5151

52-
par.make_always(clk, rst)
52+
seq.make_always(clk, rst)
5353

5454
return m
5555

tests/lib_parallel_/adder/test_lib_parallel_addr.py renamed to tests/lib_seq_/adder/test_lib_seq_addr.py

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
import lib_parallel_addr
1+
import lib_seq_addr
22

33
expected_verilog = """
44
module test;
@@ -285,7 +285,7 @@
285285
"""
286286

287287
def test():
288-
test_module = lib_parallel_addr.mkTest()
288+
test_module = lib_seq_addr.mkTest()
289289
code = test_module.to_verilog()
290290

291291
from pyverilog.vparser.parser import VerilogParser
File renamed without changes.

tests/lib_parallel_/cmp/lib_parallel_cmp.py renamed to tests/lib_seq_/cmp/lib_seq_cmp.py

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -13,12 +13,12 @@ def mkLed():
1313
x = m.Input('x', 32)
1414
y = m.OutputReg('y', initval=0)
1515

16-
par = lib.Parallel(m, 'par')
17-
par.add( y(0), cond=(x<10) )
18-
par.add( y(1), cond=(x>=10) )
19-
par.add( y(0), cond=(x>100) )
16+
seq = lib.Seq(m, 'seq')
17+
seq.add( y(0), cond=(x<10) )
18+
seq.add( y(1), cond=(x>=10) )
19+
seq.add( y(0), cond=(x>100) )
2020

21-
par.make_always(clk, rst)
21+
seq.make_always(clk, rst)
2222

2323
return m
2424

tests/lib_parallel_/cmp/test_lib_parallel_cmp.py renamed to tests/lib_seq_/cmp/test_lib_seq_cmp.py

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
import lib_parallel_cmp
1+
import lib_seq_cmp
22

33
expected_verilog = """
44
module test;
@@ -79,7 +79,7 @@
7979
"""
8080

8181
def test():
82-
test_module = lib_parallel_cmp.mkTest()
82+
test_module = lib_seq_cmp.mkTest()
8383
code = test_module.to_verilog()
8484

8585
from pyverilog.vparser.parser import VerilogParser

tests/lib_parallel_/delayed/lib_parallel_delayed.py renamed to tests/lib_seq_/delayed/lib_seq_delayed.py

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -13,16 +13,16 @@ def mkLed(numports=8, delay_amount=2):
1313
rst = m.Input('RST')
1414
led = [ m.OutputReg('led'+str(i), initval=0) for i in range(numports) ]
1515

16-
par = lib.Parallel(m, 'par')
16+
seq = lib.Seq(m, 'seq')
1717

1818
count = m.Reg('count', (numports-1).bit_length(), initval=0)
19-
par.add( count.inc() )
19+
seq.add( count.inc() )
2020

2121
for i in range(numports):
22-
par.add( led[i](1), cond=(count==i) )
23-
par.add( led[i](0), cond=(count==i), delay=delay_amount )
22+
seq.add( led[i](1), cond=(count==i) )
23+
seq.add( led[i](0), cond=(count==i), delay=delay_amount )
2424

25-
par.make_always(clk, rst)
25+
seq.make_always(clk, rst)
2626

2727
return m
2828

tests/lib_parallel_/delayed/test_lib_parallel_delayed.py renamed to tests/lib_seq_/delayed/test_lib_seq_delayed.py

Lines changed: 58 additions & 58 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
import lib_parallel_delayed
1+
import lib_seq_delayed
22

33
expected_verilog = """
44
module test;
@@ -67,124 +67,124 @@
6767
);
6868
6969
reg [3-1:0] count;
70-
reg _par_cond_0_1;
71-
reg _par_cond_0_2;
72-
reg _par_cond_1_1;
73-
reg _par_cond_1_2;
74-
reg _par_cond_2_1;
75-
reg _par_cond_2_2;
76-
reg _par_cond_3_1;
77-
reg _par_cond_3_2;
78-
reg _par_cond_4_1;
79-
reg _par_cond_4_2;
80-
reg _par_cond_5_1;
81-
reg _par_cond_5_2;
82-
reg _par_cond_6_1;
83-
reg _par_cond_6_2;
84-
reg _par_cond_7_1;
85-
reg _par_cond_7_2;
70+
reg _seq_cond_0_1;
71+
reg _seq_cond_0_2;
72+
reg _seq_cond_1_1;
73+
reg _seq_cond_1_2;
74+
reg _seq_cond_2_1;
75+
reg _seq_cond_2_2;
76+
reg _seq_cond_3_1;
77+
reg _seq_cond_3_2;
78+
reg _seq_cond_4_1;
79+
reg _seq_cond_4_2;
80+
reg _seq_cond_5_1;
81+
reg _seq_cond_5_2;
82+
reg _seq_cond_6_1;
83+
reg _seq_cond_6_2;
84+
reg _seq_cond_7_1;
85+
reg _seq_cond_7_2;
8686
8787
always @(posedge CLK) begin
8888
if(RST) begin
8989
count <= 0;
9090
led0 <= 0;
91-
_par_cond_0_1 <= 0;
92-
_par_cond_0_2 <= 0;
91+
_seq_cond_0_1 <= 0;
92+
_seq_cond_0_2 <= 0;
9393
led1 <= 0;
94-
_par_cond_1_1 <= 0;
95-
_par_cond_1_2 <= 0;
94+
_seq_cond_1_1 <= 0;
95+
_seq_cond_1_2 <= 0;
9696
led2 <= 0;
97-
_par_cond_2_1 <= 0;
98-
_par_cond_2_2 <= 0;
97+
_seq_cond_2_1 <= 0;
98+
_seq_cond_2_2 <= 0;
9999
led3 <= 0;
100-
_par_cond_3_1 <= 0;
101-
_par_cond_3_2 <= 0;
100+
_seq_cond_3_1 <= 0;
101+
_seq_cond_3_2 <= 0;
102102
led4 <= 0;
103-
_par_cond_4_1 <= 0;
104-
_par_cond_4_2 <= 0;
103+
_seq_cond_4_1 <= 0;
104+
_seq_cond_4_2 <= 0;
105105
led5 <= 0;
106-
_par_cond_5_1 <= 0;
107-
_par_cond_5_2 <= 0;
106+
_seq_cond_5_1 <= 0;
107+
_seq_cond_5_2 <= 0;
108108
led6 <= 0;
109-
_par_cond_6_1 <= 0;
110-
_par_cond_6_2 <= 0;
109+
_seq_cond_6_1 <= 0;
110+
_seq_cond_6_2 <= 0;
111111
led7 <= 0;
112-
_par_cond_7_1 <= 0;
113-
_par_cond_7_2 <= 0;
112+
_seq_cond_7_1 <= 0;
113+
_seq_cond_7_2 <= 0;
114114
end else begin
115-
if(_par_cond_0_2) begin
115+
if(_seq_cond_0_2) begin
116116
led0 <= 0;
117117
end
118-
if(_par_cond_1_2) begin
118+
if(_seq_cond_1_2) begin
119119
led1 <= 0;
120120
end
121-
if(_par_cond_2_2) begin
121+
if(_seq_cond_2_2) begin
122122
led2 <= 0;
123123
end
124-
if(_par_cond_3_2) begin
124+
if(_seq_cond_3_2) begin
125125
led3 <= 0;
126126
end
127-
if(_par_cond_4_2) begin
127+
if(_seq_cond_4_2) begin
128128
led4 <= 0;
129129
end
130-
if(_par_cond_5_2) begin
130+
if(_seq_cond_5_2) begin
131131
led5 <= 0;
132132
end
133-
if(_par_cond_6_2) begin
133+
if(_seq_cond_6_2) begin
134134
led6 <= 0;
135135
end
136-
if(_par_cond_7_2) begin
136+
if(_seq_cond_7_2) begin
137137
led7 <= 0;
138138
end
139-
_par_cond_0_2 <= _par_cond_0_1;
140-
_par_cond_1_2 <= _par_cond_1_1;
141-
_par_cond_2_2 <= _par_cond_2_1;
142-
_par_cond_3_2 <= _par_cond_3_1;
143-
_par_cond_4_2 <= _par_cond_4_1;
144-
_par_cond_5_2 <= _par_cond_5_1;
145-
_par_cond_6_2 <= _par_cond_6_1;
146-
_par_cond_7_2 <= _par_cond_7_1;
139+
_seq_cond_0_2 <= _seq_cond_0_1;
140+
_seq_cond_1_2 <= _seq_cond_1_1;
141+
_seq_cond_2_2 <= _seq_cond_2_1;
142+
_seq_cond_3_2 <= _seq_cond_3_1;
143+
_seq_cond_4_2 <= _seq_cond_4_1;
144+
_seq_cond_5_2 <= _seq_cond_5_1;
145+
_seq_cond_6_2 <= _seq_cond_6_1;
146+
_seq_cond_7_2 <= _seq_cond_7_1;
147147
count <= count + 1;
148148
if(count == 0) begin
149149
led0 <= 1;
150150
end
151-
_par_cond_0_1 <= (count == 0);
151+
_seq_cond_0_1 <= (count == 0);
152152
if(count == 1) begin
153153
led1 <= 1;
154154
end
155-
_par_cond_1_1 <= (count == 1);
155+
_seq_cond_1_1 <= (count == 1);
156156
if(count == 2) begin
157157
led2 <= 1;
158158
end
159-
_par_cond_2_1 <= (count == 2);
159+
_seq_cond_2_1 <= (count == 2);
160160
if(count == 3) begin
161161
led3 <= 1;
162162
end
163-
_par_cond_3_1 <= (count == 3);
163+
_seq_cond_3_1 <= (count == 3);
164164
if(count == 4) begin
165165
led4 <= 1;
166166
end
167-
_par_cond_4_1 <= (count == 4);
167+
_seq_cond_4_1 <= (count == 4);
168168
if(count == 5) begin
169169
led5 <= 1;
170170
end
171-
_par_cond_5_1 <= (count == 5);
171+
_seq_cond_5_1 <= (count == 5);
172172
if(count == 6) begin
173173
led6 <= 1;
174174
end
175-
_par_cond_6_1 <= (count == 6);
175+
_seq_cond_6_1 <= (count == 6);
176176
if(count == 7) begin
177177
led7 <= 1;
178178
end
179-
_par_cond_7_1 <= (count == 7);
179+
_seq_cond_7_1 <= (count == 7);
180180
end
181181
end
182182
183183
endmodule
184184
"""
185185

186186
def test():
187-
test_module = lib_parallel_delayed.mkTest()
187+
test_module = lib_seq_delayed.mkTest()
188188
code = test_module.to_verilog()
189189

190190
from pyverilog.vparser.parser import VerilogParser

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