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Commit 15400ea

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UART direction fixed
1 parent 22339ba commit 15400ea

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2 files changed

+8
-8
lines changed

2 files changed

+8
-8
lines changed

examples/thread_uart_nexys4/thread_uart_nexys4.py

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -16,8 +16,8 @@ def mkTop(clk_name='clk', rst_name='btnCpuReset'):
1616
m = Module('top')
1717
clk = m.Input(clk_name)
1818
rst = m.Input(rst_name)
19-
RsRx = m.Output('RsRx')
20-
RsTx = m.Input('RsTx')
19+
RsRx = m.Input('RsRx')
20+
RsTx = m.Output('RsTx')
2121
RsCts = m.Output('RsCts')
2222
RsRts = m.Input('RsRts')
2323
RsCts.assign(0)
@@ -37,8 +37,8 @@ def mkTop(clk_name='clk', rst_name='btnCpuReset'):
3737
ports = []
3838
ports.append(('CLK', new_clk))
3939
ports.append(('RST', new_rst))
40-
ports.append(('utx', RsRx))
41-
ports.append(('urx', RsTx))
40+
ports.append(('utx', RsTx))
41+
ports.append(('urx', RsRx))
4242
sub = Submodule(m, blinkled, name='inst_' + blinkled.name,
4343
arg_ports=ports,
4444
as_io=('sw', 'led'), as_wire=('utx', 'urx'))

examples/thread_uart_nexys4/thread_uart_nexys4.v

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -4,8 +4,8 @@ module top
44
(
55
input clk,
66
input btnCpuReset,
7-
output RsRx,
8-
input RsTx,
7+
input RsRx,
8+
output RsTx,
99
output RsCts,
1010
input RsRts,
1111
input [16-1:0] sw,
@@ -33,8 +33,8 @@ module top
3333
.RST(RST),
3434
.sw(sw),
3535
.led(led),
36-
.utx(RsRx),
37-
.urx(RsTx)
36+
.utx(RsTx),
37+
.urx(RsRx)
3838
);
3939

4040

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