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1 parent c3a597c commit 19b778fCopy full SHA for 19b778f
setup.py
@@ -12,7 +12,7 @@ def read(filename):
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setup(name='veriloggen',
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version=version,
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- description='Refactoring Tool for Verilog HDL',
+ description='A library for constructing a Verilog HDL source code in Python',
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long_description=read('README.rst'),
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keywords = 'FPGA, Verilog HDL',
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author='Shinya Takamaeda-Yamazaki',
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