Merge branch 'develop' into rc-1.4.4

Author: shtaxxx

veriloggen/stream/stream.py

@@ -94,8 +94,8 @@ def __init__(self, *nodes, **opts):
             dump_mask_name = '_stream_dump_mask_%d' % self.object_id
             dump_mask = self.module.Reg(dump_mask_name, initval=0)
             dump_step_name = '_stream_dump_step_%d' % self.object_id
-            dump_step = self.module.Reg(dump_step_name, 32,
-                                        initval=0, signed=True)
+            dump_step = self.module.Reg(dump_step_name, 32, initval=0)
+
             self.dump_enable = dump_enable
             self.dump_mask = dump_mask
             self.dump_step = dump_step
@@ -250,7 +250,7 @@ def add_dump(self, m, seq, input_vars, output_vars, all_vars):
             int(math.ceil(math.log(pipeline_depth, 10))), 1)
 
         seq(
-            self.dump_step(0)
+            self.dump_step(1)
         )
 
         for i in range(pipeline_depth + 1):
@@ -361,7 +361,7 @@ def get_name(obj):
             stage = input_var.end_stage if input_var.end_stage is not None else 0
             enable = seq.Prev(self.dump_enable, stage)
             enables.append(enable)
-            age = seq.Prev(self.dump_step, stage)
+            age = seq.Prev(self.dump_step, stage) - 1
 
             if input_var.point == 0:
                 sig_data = input_var.sig_data
@@ -394,7 +394,7 @@ def get_name(obj):
 
             enable = seq.Prev(self.dump_enable, stage)
             enables.append(enable)
-            age = seq.Prev(self.dump_step, stage)
+            age = seq.Prev(self.dump_step, stage) - 1
 
             if var.point == 0:
                 sig_data = var.sig_data
@@ -428,7 +428,7 @@ def get_name(obj):
             stage = output_var.end_stage if output_var.end_stage is not None else 0
             enable = seq.Prev(self.dump_enable, stage)
             enables.append(enable)
-            age = seq.Prev(self.dump_step, stage)
+            age = seq.Prev(self.dump_step, stage) - 1
 
             if output_var.point == 0:
                 sig_data = output_var.output_sig_data

veriloggen/thread/stream.py

@@ -1250,11 +1250,10 @@ def _setup_source_ram_dump(self, ram, var, read_enable, read_data):
 
         dump_ram_step_name = ('_stream_dump_ram_step_%d_%s' %
                               (self.object_id, name))
-        dump_ram_step = self.module.Reg(dump_ram_step_name, 32,
-                                        initval=0, signed=True)
+        dump_ram_step = self.module.Reg(dump_ram_step_name, 32, initval=0)
 
         enable = self.seq.Prev(read_enable, 2)
-        age = dump_ram_step + 1
+        age = dump_ram_step
         addr = self.seq.Prev(var.source_ram_raddr, 2)
         if hasattr(ram, 'point') and ram.point > 0:
             data = vtypes.Div(vtypes.SystemTask('itor', read_data),
@@ -1263,7 +1262,7 @@ def _setup_source_ram_dump(self, ram, var, read_enable, read_data):
             data = read_data
 
         self.seq(
-            dump_ram_step(-1)
+            dump_ram_step(0)
         )
         self.seq.If(enable)(
             dump_ram_step.inc()
@@ -1698,7 +1697,7 @@ def _setup_sink_ram_dump(self, ram, var, write_enable):
                        '[', addr_vfmt, '] = ', data_vfmt])
 
         enable = var.sink_ram_wenable
-        age = self.seq.Prev(self.dump_step, pipeline_depth + 1)
+        age = self.seq.Prev(self.dump_step, pipeline_depth + 1) - 1
         addr = var.sink_ram_waddr
         if hasattr(ram, 'point') and ram.point > 0:
             data = vtypes.Div(vtypes.SystemTask('itor', var.sink_ram_wdata),