Merge branch 'fix_stream_op_tree' into develop

Author: shtaxxx

tests/extension/stream_/add_tree/test_stream_add_tree.py

@@ -138,26 +138,26 @@
   reg signed [32-1:0] _plus_data_16;
   reg signed [32-1:0] _plus_data_18;
   reg signed [32-1:0] _plus_data_20;
-  reg signed [32-1:0] __delay_data_36;
-  reg signed [32-1:0] _plus_data_22;
-  reg signed [32-1:0] _plus_data_23;
-  reg signed [32-1:0] _plus_data_26;
-  reg signed [32-1:0] _plus_data_27;
-  reg signed [32-1:0] __delay_data_32;
-  reg signed [32-1:0] __delay_data_34;
   reg signed [32-1:0] __delay_data_37;
+  reg signed [32-1:0] _plus_data_23;
   reg signed [32-1:0] _plus_data_24;
+  reg signed [32-1:0] _plus_data_27;
   reg signed [32-1:0] _plus_data_28;
   reg signed [32-1:0] __delay_data_33;
   reg signed [32-1:0] __delay_data_35;
   reg signed [32-1:0] __delay_data_38;
   reg signed [32-1:0] _plus_data_25;
   reg signed [32-1:0] _plus_data_29;
+  reg signed [32-1:0] __delay_data_34;
+  reg signed [32-1:0] __delay_data_36;
   reg signed [32-1:0] __delay_data_39;
+  reg signed [32-1:0] _plus_data_26;
   reg signed [32-1:0] _plus_data_30;
   reg signed [32-1:0] __delay_data_40;
   reg signed [32-1:0] _plus_data_31;
-  assign zdata = _plus_data_31;
+  reg signed [32-1:0] __delay_data_41;
+  reg signed [32-1:0] _plus_data_32;
+  assign zdata = _plus_data_32;
 
   always @(posedge CLK) begin
     if(RST) begin
@@ -171,25 +171,25 @@
       _plus_data_16 <= 0;
       _plus_data_18 <= 0;
       _plus_data_20 <= 0;
-      __delay_data_36 <= 0;
-      _plus_data_22 <= 0;
-      _plus_data_23 <= 0;
-      _plus_data_26 <= 0;
-      _plus_data_27 <= 0;
-      __delay_data_32 <= 0;
-      __delay_data_34 <= 0;
       __delay_data_37 <= 0;
+      _plus_data_23 <= 0;
       _plus_data_24 <= 0;
+      _plus_data_27 <= 0;
       _plus_data_28 <= 0;
       __delay_data_33 <= 0;
       __delay_data_35 <= 0;
       __delay_data_38 <= 0;
       _plus_data_25 <= 0;
       _plus_data_29 <= 0;
+      __delay_data_34 <= 0;
+      __delay_data_36 <= 0;
       __delay_data_39 <= 0;
+      _plus_data_26 <= 0;
       _plus_data_30 <= 0;
       __delay_data_40 <= 0;
       _plus_data_31 <= 0;
+      __delay_data_41 <= 0;
+      _plus_data_32 <= 0;
     end else begin
       _plus_data_2 <= xdata + 1'sd0;
       _plus_data_4 <= xdata + 2'sd1;
@@ -201,25 +201,25 @@
       _plus_data_16 <= xdata + 4'sd7;
       _plus_data_18 <= xdata + 5'sd8;
       _plus_data_20 <= xdata + 5'sd9;
-      __delay_data_36 <= ydata;
-      _plus_data_22 <= _plus_data_2 + _plus_data_4;
-      _plus_data_23 <= _plus_data_8 + _plus_data_10;
-      _plus_data_26 <= _plus_data_12 + _plus_data_14;
-      _plus_data_27 <= _plus_data_18 + _plus_data_20;
-      __delay_data_32 <= _plus_data_6;
-      __delay_data_34 <= _plus_data_16;
-      __delay_data_37 <= __delay_data_36;
-      _plus_data_24 <= __delay_data_32 + _plus_data_23;
-      _plus_data_28 <= __delay_data_34 + _plus_data_27;
-      __delay_data_33 <= _plus_data_22;
-      __delay_data_35 <= _plus_data_26;
+      __delay_data_37 <= ydata;
+      _plus_data_23 <= _plus_data_2 + _plus_data_4;
+      _plus_data_24 <= _plus_data_8 + _plus_data_10;
+      _plus_data_27 <= _plus_data_12 + _plus_data_14;
+      _plus_data_28 <= _plus_data_18 + _plus_data_20;
+      __delay_data_33 <= _plus_data_6;
+      __delay_data_35 <= _plus_data_16;
       __delay_data_38 <= __delay_data_37;
       _plus_data_25 <= __delay_data_33 + _plus_data_24;
       _plus_data_29 <= __delay_data_35 + _plus_data_28;
+      __delay_data_34 <= _plus_data_23;
+      __delay_data_36 <= _plus_data_27;
       __delay_data_39 <= __delay_data_38;
-      _plus_data_30 <= _plus_data_25 + _plus_data_29;
+      _plus_data_26 <= __delay_data_34 + _plus_data_25;
+      _plus_data_30 <= __delay_data_36 + _plus_data_29;
       __delay_data_40 <= __delay_data_39;
-      _plus_data_31 <= _plus_data_30 + __delay_data_40;
+      _plus_data_31 <= _plus_data_26 + _plus_data_30;
+      __delay_data_41 <= __delay_data_40;
+      _plus_data_32 <= _plus_data_31 + __delay_data_41;
     end
   end
 

tests/extension/stream_/average/test_stream_average.py

@@ -136,21 +136,21 @@
   reg signed [32-1:0] _plus_data_12;
   reg signed [32-1:0] _plus_data_14;
   reg signed [32-1:0] _plus_data_16;
-  reg signed [32-1:0] __delay_data_28;
-  reg signed [32-1:0] _plus_data_18;
-  reg signed [32-1:0] _plus_data_19;
-  reg signed [32-1:0] _plus_data_21;
-  reg signed [32-1:0] _plus_data_22;
   reg signed [32-1:0] __delay_data_29;
+  reg signed [32-1:0] _plus_data_19;
   reg signed [32-1:0] _plus_data_20;
+  reg signed [32-1:0] _plus_data_22;
   reg signed [32-1:0] _plus_data_23;
   reg signed [32-1:0] __delay_data_30;
+  reg signed [32-1:0] _plus_data_21;
   reg signed [32-1:0] _plus_data_24;
   reg signed [32-1:0] __delay_data_31;
-  reg signed [32-1:0] _sra_data_25;
+  reg signed [32-1:0] _plus_data_25;
   reg signed [32-1:0] __delay_data_32;
-  reg signed [32-1:0] _plus_data_27;
-  assign zdata = _plus_data_27;
+  reg signed [32-1:0] _sra_data_26;
+  reg signed [32-1:0] __delay_data_33;
+  reg signed [32-1:0] _plus_data_28;
+  assign zdata = _plus_data_28;
 
   always @(posedge CLK) begin
     if(RST) begin
@@ -162,20 +162,20 @@
       _plus_data_12 <= 0;
       _plus_data_14 <= 0;
       _plus_data_16 <= 0;
-      __delay_data_28 <= 0;
-      _plus_data_18 <= 0;
-      _plus_data_19 <= 0;
-      _plus_data_21 <= 0;
-      _plus_data_22 <= 0;
       __delay_data_29 <= 0;
+      _plus_data_19 <= 0;
       _plus_data_20 <= 0;
+      _plus_data_22 <= 0;
       _plus_data_23 <= 0;
       __delay_data_30 <= 0;
+      _plus_data_21 <= 0;
       _plus_data_24 <= 0;
       __delay_data_31 <= 0;
-      _sra_data_25 <= 0;
+      _plus_data_25 <= 0;
       __delay_data_32 <= 0;
-      _plus_data_27 <= 0;
+      _sra_data_26 <= 0;
+      __delay_data_33 <= 0;
+      _plus_data_28 <= 0;
     end else begin
       _plus_data_2 <= xdata + 1'sd0;
       _plus_data_4 <= xdata + 2'sd1;
@@ -185,20 +185,20 @@
       _plus_data_12 <= xdata + 4'sd5;
       _plus_data_14 <= xdata + 4'sd6;
       _plus_data_16 <= xdata + 4'sd7;
-      __delay_data_28 <= ydata;
-      _plus_data_18 <= _plus_data_2 + _plus_data_4;
-      _plus_data_19 <= _plus_data_6 + _plus_data_8;
-      _plus_data_21 <= _plus_data_10 + _plus_data_12;
-      _plus_data_22 <= _plus_data_14 + _plus_data_16;
-      __delay_data_29 <= __delay_data_28;
-      _plus_data_20 <= _plus_data_18 + _plus_data_19;
-      _plus_data_23 <= _plus_data_21 + _plus_data_22;
+      __delay_data_29 <= ydata;
+      _plus_data_19 <= _plus_data_2 + _plus_data_4;
+      _plus_data_20 <= _plus_data_6 + _plus_data_8;
+      _plus_data_22 <= _plus_data_10 + _plus_data_12;
+      _plus_data_23 <= _plus_data_14 + _plus_data_16;
       __delay_data_30 <= __delay_data_29;
-      _plus_data_24 <= _plus_data_20 + _plus_data_23;
+      _plus_data_21 <= _plus_data_19 + _plus_data_20;
+      _plus_data_24 <= _plus_data_22 + _plus_data_23;
       __delay_data_31 <= __delay_data_30;
-      _sra_data_25 <= _plus_data_24 >>> 3'sd3;
+      _plus_data_25 <= _plus_data_21 + _plus_data_24;
       __delay_data_32 <= __delay_data_31;
-      _plus_data_27 <= _sra_data_25 + __delay_data_32;
+      _sra_data_26 <= _plus_data_25 >>> 3'sd3;
+      __delay_data_33 <= __delay_data_32;
+      _plus_data_28 <= _sra_data_26 + __delay_data_33;
     end
   end
 

veriloggen/stream/stypes.py

@@ -1854,7 +1854,7 @@ def op_tree(op, initval, latency, *args):
 def PlusN(*args):
     for arg in args:
         if isinstance(arg, _Numeric) and arg.point != 0:
-            ret = op_tree(Plus, vtypes.Int(0, signed=True), 0, *args)
+            ret = op_tree(Plus, Int(0, signed=True), 0, *args)
             ret.latency = 1
             return ret
 
@@ -1866,7 +1866,7 @@ def AddN(*args):
 
 
 def AddTree(*args):
-    return op_tree(Plus, vtypes.Int(0, signed=True), None, *args)
+    return op_tree(Plus, Int(0, signed=True), None, *args)
 
 
 def Max(*args):