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Merge branch 'feature_axi_stream' into develop
2 parents 6aae207 + 2e9c479 commit 69b3c98

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‎tests/extension/thread_/axi_dma_axim2/Makefile

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TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py)
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ARGS=
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PYTHON=python3
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#PYTHON=python
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#OPT=-m pdb
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#OPT=-m cProfile -s time
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#OPT=-m cProfile -o profile.rslt
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.PHONY: all
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all: test
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.PHONY: run
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run:
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$(PYTHON) $(OPT) $(TARGET) $(ARGS)
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.PHONY: test
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test:
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$(PYTHON) -m pytest -vv
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.PHONY: check
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check:
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$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
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iverilog -tnull -Wall tmp.v
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rm -f tmp.v
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.PHONY: clean
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clean:
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rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd

‎tests/extension/thread_/axi_dma_axim2/test_thread_axi_dma_axim2.py

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from __future__ import absolute_import
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from __future__ import print_function
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import os
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import veriloggen
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import thread_axi_dma_axim2
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def test(request):
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veriloggen.reset()
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simtype = request.config.getoption('--sim')
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rslt = thread_axi_dma_axim2.run(filename=None, simtype=simtype,
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outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out')
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verify_rslt = rslt.splitlines()[-1]
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assert(verify_rslt == '# verify: PASSED')

‎tests/extension/thread_/axi_dma_axim2/thread_axi_dma_axim2.py

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from __future__ import absolute_import
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from __future__ import print_function
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import sys
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import os
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# the next line can be removed after installation
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sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(
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os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))))
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from veriloggen import *
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import veriloggen.thread as vthread
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import veriloggen.types.axi as axi
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def mkLed():
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m = Module('blinkled')
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clk = m.Input('CLK')
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rst = m.Input('RST')
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datawidth = 32
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addrwidth = 10
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myaxi = vthread.AXIM2(m, 'myaxi', clk, rst, datawidth,
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num_cmd_delay=1, num_data_delay=1)
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myram = vthread.RAM(m, 'myram', clk, rst, datawidth, addrwidth,
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numports=2)
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all_ok = m.TmpReg(initval=0)
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def blink(size):
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all_ok.value = True
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for i in range(4):
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print('# iter %d start' % i)
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# Test for 4KB boundary check
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offset = i * 1024 * 16 + (myaxi.boundary_size - 4)
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body(size, offset)
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print('# iter %d end' % i)
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if all_ok:
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print('# verify: PASSED')
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else:
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print('# verify: FAILED')
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vthread.finish()
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def body(size, offset):
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# write
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for i in range(size):
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wdata = i + 100
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myram.write(i, wdata)
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laddr = 0
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gaddr = offset
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myaxi.dma_write(myram, laddr, gaddr, size, port=0)
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print('dma_write: [%d] -> [%d]' % (laddr, gaddr))
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# write
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for i in range(size):
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wdata = i + 1000
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myram.write(i, wdata)
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laddr = 0
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gaddr = (size + size) * 4 + offset
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myaxi.dma_write(myram, laddr, gaddr, size, port=1)
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print('dma_write: [%d] -> [%d]' % (laddr, gaddr))
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# read
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laddr = 0
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gaddr = offset
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myaxi.dma_read(myram, laddr, gaddr, size, port=1)
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print('dma_read: [%d] <- [%d]' % (laddr, gaddr))
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for i in range(size):
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rdata = myram.read(i)
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if vthread.verilog.NotEql(rdata, i + 100):
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print('rdata[%d] = %d' % (i, rdata))
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all_ok.value = False
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# read
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laddr = 0
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gaddr = (size + size) * 4 + offset
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myaxi.dma_read(myram, laddr, gaddr, size, port=0)
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print('dma_read: [%d] <- [%d]' % (laddr, gaddr))
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for i in range(size):
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rdata = myram.read(i)
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if vthread.verilog.NotEql(rdata, i + 1000):
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print('rdata[%d] = %d' % (i, rdata))
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all_ok.value = False
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th = vthread.Thread(m, 'th_blink', clk, rst, blink)
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fsm = th.start(16)
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return m
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def mkTest(memimg_name=None):
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m = Module('test')
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# target instance
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led = mkLed()
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# copy paras and ports
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params = m.copy_params(led)
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ports = m.copy_sim_ports(led)
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clk = ports['CLK']
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rst = ports['RST']
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memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memimg_name=memimg_name)
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memory.connect(ports, 'myaxi')
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uut = m.Instance(led, 'uut',
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params=m.connect_params(led),
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ports=m.connect_ports(led))
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# simulation.setup_waveform(m, uut)
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simulation.setup_clock(m, clk, hperiod=5)
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init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
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init.add(
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Delay(1000000),
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Systask('finish'),
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)
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return m
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def run(filename='tmp.v', simtype='iverilog', outputfile=None):
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if outputfile is None:
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outputfile = os.path.splitext(os.path.basename(__file__))[0] + '.out'
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memimg_name = 'memimg_' + outputfile
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test = mkTest(memimg_name=memimg_name)
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if filename is not None:
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test.to_verilog(filename)
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sim = simulation.Simulator(test, sim=simtype)
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rslt = sim.run(outputfile=outputfile)
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lines = rslt.splitlines()
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if simtype == 'verilator' and lines[-1].startswith('-'):
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rslt = '\n'.join(lines[:-1])
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return rslt
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if __name__ == '__main__':
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rslt = run(filename='tmp.v')
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print(rslt)

‎tests/extension/thread_/axi_dma_axim2_narrow/Makefile

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TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py)
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ARGS=
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PYTHON=python3
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#PYTHON=python
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#OPT=-m pdb
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#OPT=-m cProfile -s time
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#OPT=-m cProfile -o profile.rslt
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.PHONY: all
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all: test
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.PHONY: run
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run:
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$(PYTHON) $(OPT) $(TARGET) $(ARGS)
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.PHONY: test
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test:
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$(PYTHON) -m pytest -vv
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.PHONY: check
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check:
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$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
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iverilog -tnull -Wall tmp.v
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rm -f tmp.v
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.PHONY: clean
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clean:
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rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd

‎tests/extension/thread_/axi_dma_axim2_narrow/test_thread_axi_dma_axim2_narrow.py

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from __future__ import absolute_import
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from __future__ import print_function
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import os
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import veriloggen
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import thread_axi_dma_axim2_narrow
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def test(request):
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veriloggen.reset()
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simtype = request.config.getoption('--sim')
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rslt = thread_axi_dma_axim2_narrow.run(filename=None, simtype=simtype,
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outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out')
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verify_rslt = rslt.splitlines()[-1]
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assert(verify_rslt == '# verify: PASSED')

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