Merge branch 'develop' into rc-1.4.1

shtaxxx · shtaxxx · commit 6b11cde07661 · 2018-11-21T19:37:34.000+09:00
diff --git a/veriloggen/thread/stream.py b/veriloggen/thread/stream.py
@@ -1241,6 +1241,9 @@ def _setup_source_ram_dump(self, ram, var, read_enable, read_data):
         self.seq.If(enable)(
             dump_ram_step.inc()
         )
+        self.seq.If(self.dump_enable)(
+            dump_ram_step.inc()
+        )
 
         self.seq.If(enable)(
             vtypes.Display(fmt, dump_ram_step, age, addr, data)

Original file line number	Diff line number	Diff line change
`@@ -1241,6 +1241,9 @@ def _setup_source_ram_dump(self, ram, var, read_enable, read_data):`
`1241`	`1241`	`self.seq.If(enable)(`
`1242`	`1242`	`dump_ram_step.inc()`
`1243`	`1243`	`)`
	`1244`	`+ self.seq.If(self.dump_enable)(`
	`1245`	`+ dump_ram_step.inc()`
	`1246`	`+ )`
`1244`	`1247`
`1245`	`1248`	`self.seq.If(enable)(`
`1246`	`1249`	`vtypes.Display(fmt, dump_ram_step, age, addr, data)`