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1 parent 79251c2 commit 6f80909Copy full SHA for 6f80909
veriloggen/lib/simulation.py
@@ -42,4 +42,4 @@ def setup_reset(m, reset, *statement, **kwargs):
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return ret
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def next_clock(clk):
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- return vtypes.Event(vtypes.Posedge(clk))
+ return ( vtypes.Event(vtypes.Posedge(clk)), vtypes.Delay(1) )
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