Merge branch 'develop' into feature_axi_stream

Author: shtaxxx

veriloggen/stream/stypes.py

@@ -3493,10 +3493,10 @@ def _implement(self, m, seq, svalid=None, senable=None):
                              (self.latency, 2))
 
         if len(self.args) == 3 and self.latency == 2:
-            raise ValueError('latency = 2 is not allowed, if when option is used.')
+            raise ValueError("latency = 2 is not allowed, if 'when' option is used.")
 
         if senable is not None and self.latency == 2:
-            raise NotImplementedError('senable is not supported, if when option is used.')
+            raise NotImplementedError("senable is not supported, if 'when' option is used.")
 
         datawidth = self.bit_length()
         signed = self.get_signed()
@@ -3573,9 +3573,6 @@ def _implement(self, m, seq, svalid=None, senable=None):
             raise ValueError("Latency mismatch '%d' != '%s'" %
                              (self.latency, 1))
 
-        if senable is not None:
-            raise NotImplementedError('senable is not supported.')
-
         self.sig_data = vtypes.Int(0)
 
     @property