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Updated the result check codes for the updated iverilog.
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examples/axi_stream_ultra96v2_pynq/ultra96v2_pynq/run_on_pynq.py

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -81,4 +81,3 @@
8181

8282
diff_sum = np.sum(expected - dst)
8383
print(diff_sum)
84-

examples/chatter_clear/test_chatter_clear.py

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -185,6 +185,7 @@
185185
endmodule
186186
"""
187187

188+
188189
def test():
189190
veriloggen.reset()
190191
test_module = chatter_clear.mkTest()

examples/counter/test_counter.py

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -90,6 +90,7 @@
9090
endmodule
9191
"""
9292

93+
9394
def test():
9495
veriloggen.reset()
9596
test_module = counter.mkTest()

examples/led/test_led.py

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -82,6 +82,7 @@
8282
endmodule
8383
"""
8484

85+
8586
def test():
8687
veriloggen.reset()
8788
test_module = led.mkTest()

examples/manyled/manyled.py

Lines changed: 7 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,7 @@
88

99
from veriloggen import *
1010

11+
1112
def mkLed():
1213
m = Module('blinkled')
1314
width = m.Parameter('WIDTH', 8)
@@ -16,8 +17,8 @@ def mkLed():
1617

1718
# function to add an LED port
1819
def add_led(postfix, limit=1024):
19-
led = m.OutputReg('LED'+postfix, width)
20-
count = m.Reg('count'+postfix, 32)
20+
led = m.OutputReg('LED' + postfix, width)
21+
count = m.Reg('count' + postfix, 32)
2122

2223
m.Always(Posedge(clk))(
2324
If(rst)(
@@ -29,7 +30,7 @@ def add_led(postfix, limit=1024):
2930
count(count + 1)
3031
)
3132
))
32-
33+
3334
m.Always(Posedge(clk))(
3435
If(rst)(
3536
led(0)
@@ -41,10 +42,11 @@ def add_led(postfix, limit=1024):
4142

4243
# call 'add_led' to add LED ports
4344
for i in range(4):
44-
add_led('_' + str(i), limit=i*10 + 10)
45-
45+
add_led('_' + str(i), limit=i * 10 + 10)
46+
4647
return m
4748

49+
4850
if __name__ == '__main__':
4951
led = mkLed()
5052
verilog = led.to_verilog()

examples/manyled/test_manyled.py

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -103,6 +103,7 @@
103103
endmodule
104104
"""
105105

106+
106107
def test():
107108
veriloggen.reset()
108109
test_module = manyled.mkLed()

examples/read_verilog_code/read_verilog_code.py

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -43,23 +43,25 @@
4343
endmodule
4444
'''
4545

46+
4647
def mkLed():
4748
modules = from_verilog.read_verilog_module_str(led_v)
4849
m = modules['blinkled']
49-
50+
5051
# change the module name
5152
m.name = 'modified_led'
52-
53+
5354
# add new statements
5455
enable = m.Input('enable')
5556
busy = m.Output('busy')
5657

5758
old_statement = m.always[0].statement[0].false_statement
5859
m.always[0].statement[0].false_statement = If(enable)(*old_statement)
59-
m.Assign( busy(m.variable['count'] < 1023) )
60-
60+
m.Assign(busy(m.variable['count'] < 1023))
61+
6162
return m
6263

64+
6365
if __name__ == '__main__':
6466
led = mkLed()
6567
verilog = led.to_verilog()

examples/read_verilog_code/test_read_verilog_code.py

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -40,6 +40,7 @@
4040
endmodule
4141
"""
4242

43+
4344
def test():
4445
veriloggen.reset()
4546
test_module = read_verilog_code.mkLed()

examples/regchain/regchain.py

Lines changed: 67 additions & 64 deletions
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,7 @@
88

99
from veriloggen import *
1010

11+
1112
def mkRegChain(length=120, width=8):
1213
m = Module("reg_chain")
1314

@@ -19,97 +20,98 @@ def mkRegChain(length=120, width=8):
1920
seq = Seq(m, 'seq', clk, rst)
2021

2122
update_cond_value = m.TmpReg(3, initval=0)
22-
seq( update_cond_value(sw[0:3]) )
23+
seq(update_cond_value(sw[0:3]))
2324

2425
area_size = m.TmpReg(2, initval=0)
25-
seq( area_size(sw[3:5]) )
26-
26+
seq(area_size(sw[3:5]))
27+
2728
count = m.TmpReg(2, initval=0)
28-
seq( count.inc() )
29-
29+
seq(count.inc())
30+
3031
update_cond = m.TmpReg(initval=0)
31-
seq( update_cond(count < update_cond_value) )
32+
seq(update_cond(count < update_cond_value))
3233

3334
orig = m.TmpReg(width, initval=0)
3435
prev = orig
3536

3637
regs = []
37-
38+
3839
for i in range(length):
3940
area_id = i // (length // 4)
4041
r = m.TmpReg(width, initval=0)
4142
regs.append(r)
42-
seq.If(AndList(update_cond, area_id <= area_size))( r(prev + 1) )
43+
seq.If(AndList(update_cond, area_id <= area_size))(r(prev + 1))
4344
prev = r
4445

45-
seq.If(AndList(update_cond, area_size==0))( orig(regs[1*length//4-1] + 3) )
46-
seq.If(AndList(update_cond, area_size==1))( orig(regs[2*length//4-1] + 2) )
47-
seq.If(AndList(update_cond, area_size==2))( orig(regs[3*length//4-1] + 1) )
48-
seq.If(AndList(update_cond, area_size==3))( orig(regs[4*length//4-1] + 0) )
46+
seq.If(AndList(update_cond, area_size == 0))(orig(regs[1 * length // 4 - 1] + 3))
47+
seq.If(AndList(update_cond, area_size == 1))(orig(regs[2 * length // 4 - 1] + 2))
48+
seq.If(AndList(update_cond, area_size == 2))(orig(regs[3 * length // 4 - 1] + 1))
49+
seq.If(AndList(update_cond, area_size == 3))(orig(regs[4 * length // 4 - 1] + 0))
4950

5051
seq.make_always()
51-
52-
m.Assign( dout(orig) )
52+
53+
m.Assign(dout(orig))
5354

5455
return m
5556

57+
5658
def mkTest(length=120, width=8):
5759
m = Module('test')
58-
60+
5961
main = mkRegChain(length, width)
6062
params = m.copy_params(main)
6163
ports = m.copy_sim_ports(main)
62-
64+
6365
clk = ports['CLK']
6466
rst = ports['RST']
6567
sw = ports['sw']
6668
dout = ports['dout']
6769

6870
fsm = FSM(m, 'fsm', clk, rst)
6971
count = m.TmpReg(32, initval=0)
70-
71-
fsm( sw((3 << 3) | 4) )
72-
fsm( count.inc() )
73-
fsm.If(count==2000)( count(0) )
74-
fsm.goto_next(count==2000)
75-
76-
fsm( sw((2 << 3) | 4) )
77-
fsm( count.inc() )
78-
fsm.If(count==2000)( count(0) )
79-
fsm.goto_next(count==2000)
80-
81-
fsm( sw((1 << 3) | 4) )
82-
fsm( count.inc() )
83-
fsm.If(count==2000)( count(0) )
84-
fsm.goto_next(count==2000)
85-
86-
fsm( sw((0 << 3) | 4) )
87-
fsm( count.inc() )
88-
fsm.If(count==2000)( count(0) )
89-
fsm.goto_next(count==2000)
90-
91-
fsm( sw((2 << 3) | 3) )
92-
fsm( count.inc() )
93-
fsm.If(count==2000)( count(0) )
94-
fsm.goto_next(count==2000)
95-
96-
fsm( sw((2 << 3) | 2) )
97-
fsm( count.inc() )
98-
fsm.If(count==2000)( count(0) )
99-
fsm.goto_next(count==2000)
100-
101-
fsm( sw((2 << 3) | 1) )
102-
fsm( count.inc() )
103-
fsm.If(count==2000)( count(0) )
104-
fsm.goto_next(count==2000)
105-
106-
fsm( sw((2 << 3) | 0) )
107-
fsm( count.inc() )
108-
fsm.If(count==2000)( count(0) )
109-
fsm.goto_next(count==2000)
72+
73+
fsm(sw((3 << 3) | 4))
74+
fsm(count.inc())
75+
fsm.If(count == 2000)(count(0))
76+
fsm.goto_next(count == 2000)
77+
78+
fsm(sw((2 << 3) | 4))
79+
fsm(count.inc())
80+
fsm.If(count == 2000)(count(0))
81+
fsm.goto_next(count == 2000)
82+
83+
fsm(sw((1 << 3) | 4))
84+
fsm(count.inc())
85+
fsm.If(count == 2000)(count(0))
86+
fsm.goto_next(count == 2000)
87+
88+
fsm(sw((0 << 3) | 4))
89+
fsm(count.inc())
90+
fsm.If(count == 2000)(count(0))
91+
fsm.goto_next(count == 2000)
92+
93+
fsm(sw((2 << 3) | 3))
94+
fsm(count.inc())
95+
fsm.If(count == 2000)(count(0))
96+
fsm.goto_next(count == 2000)
97+
98+
fsm(sw((2 << 3) | 2))
99+
fsm(count.inc())
100+
fsm.If(count == 2000)(count(0))
101+
fsm.goto_next(count == 2000)
102+
103+
fsm(sw((2 << 3) | 1))
104+
fsm(count.inc())
105+
fsm.If(count == 2000)(count(0))
106+
fsm.goto_next(count == 2000)
107+
108+
fsm(sw((2 << 3) | 0))
109+
fsm(count.inc())
110+
fsm.If(count == 2000)(count(0))
111+
fsm.goto_next(count == 2000)
110112

111113
fsm.make_always()
112-
114+
113115
uut = m.Instance(main, 'uut',
114116
params=m.connect_params(main),
115117
ports=m.connect_ports(main))
@@ -119,30 +121,31 @@ def mkTest(length=120, width=8):
119121
init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
120122

121123
nclk = simulation.next_clock
122-
124+
123125
init.add(
124126
sw(0),
125127
Delay(1000 * 200),
126128
Systask('finish'),
127129
)
128130

129131
return m
130-
132+
133+
131134
if __name__ == '__main__':
132135
main = mkRegChain(length=120)
133136
verilog = main.to_verilog('tmp.v')
134137
print(verilog)
135138

136139
#test = mkTest()
137140
#verilog = test.to_verilog('tmp.v')
138-
#print(verilog)
141+
# print(verilog)
139142

140143
# run simulator (Icarus Verilog)
141144
#sim = simulation.Simulator(test)
142-
#rslt = sim.run() # display=False
145+
# rslt = sim.run() # display=False
143146
##rslt = sim.run(display=True)
144-
#print(rslt)
147+
# print(rslt)
145148

146149
# launch waveform viewer (GTKwave)
147-
#sim.view_waveform() # background=False
148-
#sim.view_waveform(background=True)
150+
# sim.view_waveform() # background=False
151+
# sim.view_waveform(background=True)

examples/regchain/test_regchain.py

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -650,6 +650,7 @@
650650
endmodule
651651
"""
652652

653+
653654
def test():
654655
veriloggen.reset()
655656
test_module = regchain.mkRegChain(length=120)

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