Merge branch '1.2.3-rc'

Author: shtaxxx

tests/extension/thread_/axi_dma_long_narrow/thread_axi_dma_long_narrow.py

@@ -84,7 +84,7 @@ def body(size, offset):
                 all_ok.value = False
 
     th = vthread.Thread(m, 'th_blink', clk, rst, blink)
-    fsm = th.start(256 + 256 + 64)
+    fsm = th.start(256 + 256 + 66 + 1)
 
     return m
 

tests/extension/thread_/axi_dma_long_wide/thread_axi_dma_long_wide.py

@@ -28,7 +28,7 @@ def blink(size):
         all_ok.value = True
 
         # Test for 4KB boundary check
-        offset = myaxi.boundary_size - 16
+        offset = myaxi.boundary_size - memory_datawidth // 8
         body(size, offset)
 
         if all_ok:
@@ -84,7 +84,7 @@ def body(size, offset):
                 all_ok.value = False
 
     th = vthread.Thread(m, 'th_blink', clk, rst, blink)
-    fsm = th.start(256 + 256 + 64)
+    fsm = th.start(256 + 256 + 64 + 1)
 
     return m
 

tests/extension/thread_/axi_dma_narrow/thread_axi_dma_narrow.py

@@ -89,7 +89,7 @@ def body(size, offset):
                 all_ok.value = False
 
     th = vthread.Thread(m, 'th_blink', clk, rst, blink)
-    fsm = th.start(16)
+    fsm = th.start(17)
 
     return m
 

tests/extension/thread_/axi_dma_wide/thread_axi_dma_wide.py

@@ -30,7 +30,7 @@ def blink(size):
         for i in range(4):
             print('# iter %d start' % i)
             # Test for 4KB boundary check
-            offset = i * 1024 * 16 + (myaxi.boundary_size - 16)
+            offset = i * 1024 * 16 + (myaxi.boundary_size - memory_datawidth // 8)
             body(size, offset)
             print('# iter %d end' % i)
 
@@ -87,7 +87,7 @@ def body(size, offset):
                 all_ok.value = False
 
     th = vthread.Thread(m, 'th_blink', clk, rst, blink)
-    fsm = th.start(16)
+    fsm = th.start(17)
 
     return m
 

veriloggen/thread/axi.py

@@ -618,9 +618,12 @@ def _synthesize_read_fsm_wide(self, ram, port, ram_method, ram_datawidth):
                 'axi.datawidth must be multiple number of ram_datawidth')
 
         pack_size = self.datawidth // ram_datawidth
-        dma_size = (self.read_size >> int(math.log(pack_size, 2))
-                    if math.log(pack_size, 2) % 1.0 == 0.0 else
-                    int(size // pack_size))
+        shamt = int(math.log(pack_size, 2))
+        res = vtypes.Mux(
+            vtypes.And(self.read_size, 2 ** shamt - 1) > 0, 1, 0)
+        dma_size = (self.read_size >> shamt) + res
+
+        actual_read_size = dma_size << shamt
 
         op_id = self._get_read_op_id(ram, port, ram_method)
         port = vtypes.to_int(port)
@@ -642,7 +645,7 @@ def _synthesize_read_fsm_wide(self, ram, port, ram_method, ram_datawidth):
             fsm.set_index(0)
             wdata, wvalid, w = self._get_op_write_dataflow(ram_datawidth)
             cond = vtypes.Ands(self.read_start, self.read_op_sel == op_id)
-            ram_method(port, self.read_local_addr, w, self.read_size,
+            ram_method(port, self.read_local_addr, w, actual_read_size,
                        stride=self.read_local_stride, cond=cond)
 
             fsm.If(cond).goto_next()
@@ -694,7 +697,7 @@ def _synthesize_read_fsm_wide(self, ram, port, ram_method, ram_datawidth):
         # state 0
         wdata, wvalid, w = self._get_op_write_dataflow(ram_datawidth)
         cond = vtypes.Ands(self.read_start, self.read_op_sel == op_id)
-        ram_method(port, self.read_local_addr, w, self.read_size,
+        ram_method(port, self.read_local_addr, w, actual_read_size,
                    stride=self.read_local_stride, cond=cond)
 
         fsm.If(self.read_start)(
@@ -1204,9 +1207,12 @@ def _synthesize_write_fsm_wide(self, ram, port, ram_method, ram_datawidth):
                 'axi.datawidth must be multiple number of ram_datawidth')
 
         pack_size = self.datawidth // ram_datawidth
-        dma_size = (self.write_size >> int(math.log(pack_size, 2))
-                    if math.log(pack_size, 2) % 1.0 == 0.0 else
-                    int(size // pack_size))
+        shamt = int(math.log(pack_size, 2))
+        res = vtypes.Mux(
+            vtypes.And(self.write_size, 2 ** shamt - 1) > 0, 1, 0)
+        dma_size = (self.write_size >> shamt) + res
+
+        actual_write_size = dma_size << shamt
 
         op_id = self._get_write_op_id(ram, port, ram_method)
         port = vtypes.to_int(port)
@@ -1229,7 +1235,7 @@ def _synthesize_write_fsm_wide(self, ram, port, ram_method, ram_datawidth):
             fsm.set_index(0)
             cond = vtypes.Ands(self.write_start, self.write_op_sel == op_id)
             data, last, done = ram_method(
-                port, self.write_local_addr, self.write_size,
+                port, self.write_local_addr, actual_write_size,
                 stride=self.write_local_stride, cond=cond, signed=False)
 
             if self.num_data_delay > 0:
@@ -1284,7 +1290,7 @@ def _synthesize_write_fsm_wide(self, ram, port, ram_method, ram_datawidth):
         # state 0
         cond = vtypes.Ands(self.write_start, self.write_op_sel == op_id)
         data, last, done = ram_method(
-            port, self.write_local_addr, self.write_size,
+            port, self.write_local_addr, actual_write_size,
             stride=self.write_local_stride, cond=cond, signed=False)
 
         if self.num_data_delay > 0:

veriloggen/utils/VERSION

@@ -1 +1 @@
-1.2.2
+1.2.3