Merge branch 'develop' into rc-1.5.2

Author: shtaxxx

veriloggen/thread/fixed.py

@@ -45,10 +45,9 @@ def reinterpret_cast_to_fixed(fsm, value, point, signed=True):
     return fxd.reinterpret_cast_to_fixed(value, point, signed)
 
 
-def fixed_to_int(fsm, value, point, signed=True):
+def fixed_to_int(fsm, value, point):
     point = vtypes.raw_value(point)
-    signed = vtypes.raw_value(signed)
-    return fxd.fixed_to_int(value, point, signed)
+    return fxd.fixed_to_int(value, point)
 
 
 def fixed_to_real(fsm, value, point, signed=True):

veriloggen/types/fixed.py

@@ -126,11 +126,11 @@ def fixed_to_int(value, point):
 
     if isinstance(value, (int, bool, float)) and isinstance(point, int):
         mag = 2 ** point
-        return int(value / mag)
+        return value // mag
 
     if isinstance(value, (int, bool, float)):
         mag = vtypes.Int(2) ** point
-        return vtypes.Int(value) / mag
+        return vtypes.Int(value) // mag
 
     signed = vtypes.get_signed(value)
     return shift_right(value, point, signed)