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[RISCV] Combine vslide{up,down} x, poison -> x (llvm#169013)
The motivation for this is that it would be useful to express a vslideup/vslidedown in a target independent way e.g. from the loop vectorizer. We can do this today with @llvm.vector.splice by setting one operand to poison: - A slide down can be achieved with @llvm.vector.splice(%x, poison, slideamt) - A slide up can be done by @llvm.vector.splice(poison, %x, -slideamt) E.g.: splice(<a,b,c,d>, poison, 3) = <d,poison,poison,poison> splice(poison, <a,b,c,d>, -3) = <poison,poison,poison,a> These splices get lowered to a vslideup + vslidedown pair with one of the vs2s being poison. We can optimize this away so that we are just left with a single slideup/slidedown.
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‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp‎

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@@ -21802,6 +21802,11 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
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return N->getOperand(0);
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break;
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}
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case RISCVISD::VSLIDEDOWN_VL:
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case RISCVISD::VSLIDEUP_VL:
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if (N->getOperand(1)->isUndef())
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return N->getOperand(0);
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break;
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case RISCVISD::VSLIDE1UP_VL:
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case RISCVISD::VFSLIDE1UP_VL: {
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using namespace SDPatternMatch;

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vector-splice.ll‎

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@@ -0,0 +1,91 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc -mtriple riscv32 -mattr=+v < %s | FileCheck %s
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; RUN: llc -mtriple riscv64 -mattr=+v < %s | FileCheck %s
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; RUN: llc -mtriple riscv32 -mattr=+v,+vl-dependent-latency < %s | FileCheck %s
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; RUN: llc -mtriple riscv64 -mattr=+v,+vl-dependent-latency < %s | FileCheck %s
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define <4 x i32> @splice_v4i32_slidedown(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: splice_v4i32_slidedown:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; CHECK-NEXT: vrgather.vi v9, v8, 3
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; CHECK-NEXT: vmv.v.v v8, v9
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; CHECK-NEXT: ret
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%res = call <4 x i32> @llvm.vector.splice(<4 x i32> %a, <4 x i32> poison, i32 3)
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ret <4 x i32> %res
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}
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define <4 x i32> @splice_4i32_slideup(<4 x i32> %a) {
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; CHECK-LABEL: splice_4i32_slideup:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; CHECK-NEXT: vrgather.vi v9, v8, 0
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; CHECK-NEXT: vmv.v.v v8, v9
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; CHECK-NEXT: ret
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%res = call <4 x i32> @llvm.vector.splice(<4 x i32> poison, <4 x i32> %a, i32 -3)
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ret <4 x i32> %res
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}
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define <8 x i32> @splice_v8i32_slidedown(<8 x i32> %a, <8 x i32> %b) {
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; CHECK-LABEL: splice_v8i32_slidedown:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
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; CHECK-NEXT: vslidedown.vi v8, v8, 3
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; CHECK-NEXT: ret
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%res = call <8 x i32> @llvm.vector.splice(<8 x i32> %a, <8 x i32> poison, i32 3)
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ret <8 x i32> %res
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}
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define <8 x i32> @splice_v8i32_slideup(<8 x i32> %a) {
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; CHECK-LABEL: splice_v8i32_slideup:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
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; CHECK-NEXT: vslideup.vi v10, v8, 3
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; CHECK-NEXT: vmv.v.v v8, v10
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; CHECK-NEXT: ret
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%res = call <8 x i32> @llvm.vector.splice(<8 x i32> poison, <8 x i32> %a, i32 -3)
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ret <8 x i32> %res
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}
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define <4 x i32> @splice_v4i32_slidedown_undef(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: splice_v4i32_slidedown_undef:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; CHECK-NEXT: vrgather.vi v9, v8, 3
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; CHECK-NEXT: vmv.v.v v8, v9
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; CHECK-NEXT: ret
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%res = call <4 x i32> @llvm.vector.splice(<4 x i32> %a, <4 x i32> undef, i32 3)
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ret <4 x i32> %res
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}
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define <4 x i32> @splice_4i32_slideup_undef(<4 x i32> %a) {
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; CHECK-LABEL: splice_4i32_slideup_undef:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; CHECK-NEXT: vrgather.vi v9, v8, 0
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; CHECK-NEXT: vmv.v.v v8, v9
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; CHECK-NEXT: ret
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%res = call <4 x i32> @llvm.vector.splice(<4 x i32> undef, <4 x i32> %a, i32 -3)
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ret <4 x i32> %res
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}
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define <8 x i32> @splice_v8i32_slidedown_undef(<8 x i32> %a, <8 x i32> %b) {
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; CHECK-LABEL: splice_v8i32_slidedown_undef:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
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; CHECK-NEXT: vslidedown.vi v8, v8, 3
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; CHECK-NEXT: ret
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%res = call <8 x i32> @llvm.vector.splice(<8 x i32> %a, <8 x i32> undef, i32 3)
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ret <8 x i32> %res
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}
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define <8 x i32> @splice_v8i32_slideup_undef(<8 x i32> %a) {
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; CHECK-LABEL: splice_v8i32_slideup_undef:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
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; CHECK-NEXT: vslideup.vi v10, v8, 3
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; CHECK-NEXT: vmv.v.v v8, v10
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; CHECK-NEXT: ret
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%res = call <8 x i32> @llvm.vector.splice(<8 x i32> undef, <8 x i32> %a, i32 -3)
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ret <8 x i32> %res
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}

‎llvm/test/CodeGen/RISCV/rvv/vector-splice.ll‎

Lines changed: 60 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4247,4 +4247,64 @@ define <vscale x 8 x double> @splice_nxv8f64_offset_max(<vscale x 8 x double> %a
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ret <vscale x 8 x double> %res
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}
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define <vscale x 2 x i32> @splice_nxv2i32_slidedown(<vscale x 2 x i32> %a) #0 {
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; NOVLDEP-LABEL: splice_nxv2i32_slidedown:
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; NOVLDEP: # %bb.0:
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; NOVLDEP-NEXT: vsetvli a0, zero, e32, m1, ta, ma
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; NOVLDEP-NEXT: vslidedown.vi v8, v8, 3
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; NOVLDEP-NEXT: ret
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;
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; VLDEP-LABEL: splice_nxv2i32_slidedown:
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; VLDEP: # %bb.0:
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; VLDEP-NEXT: csrr a0, vlenb
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; VLDEP-NEXT: srli a0, a0, 2
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; VLDEP-NEXT: addi a0, a0, -3
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; VLDEP-NEXT: vsetvli zero, a0, e32, m1, ta, ma
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; VLDEP-NEXT: vslidedown.vi v8, v8, 3
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; VLDEP-NEXT: ret
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%res = call <vscale x 2 x i32> @llvm.vector.splice(<vscale x 2 x i32> %a, <vscale x 2 x i32> poison, i32 3)
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ret <vscale x 2 x i32> %res
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}
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define <vscale x 2 x i32> @splice_nxv2i32_slideup(<vscale x 2 x i32> %a) #0 {
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; CHECK-LABEL: splice_nxv2i32_slideup:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
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; CHECK-NEXT: vslideup.vi v9, v8, 3
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; CHECK-NEXT: vmv.v.v v8, v9
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; CHECK-NEXT: ret
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%res = call <vscale x 2 x i32> @llvm.vector.splice(<vscale x 2 x i32> poison, <vscale x 2 x i32> %a, i32 -3)
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ret <vscale x 2 x i32> %res
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}
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define <vscale x 2 x i32> @splice_nxv2i32_slidedown_undef(<vscale x 2 x i32> %a) #0 {
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; NOVLDEP-LABEL: splice_nxv2i32_slidedown_undef:
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; NOVLDEP: # %bb.0:
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; NOVLDEP-NEXT: vsetvli a0, zero, e32, m1, ta, ma
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; NOVLDEP-NEXT: vslidedown.vi v8, v8, 3
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; NOVLDEP-NEXT: ret
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;
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; VLDEP-LABEL: splice_nxv2i32_slidedown_undef:
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; VLDEP: # %bb.0:
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; VLDEP-NEXT: csrr a0, vlenb
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; VLDEP-NEXT: srli a0, a0, 2
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; VLDEP-NEXT: addi a0, a0, -3
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; VLDEP-NEXT: vsetvli zero, a0, e32, m1, ta, ma
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; VLDEP-NEXT: vslidedown.vi v8, v8, 3
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; VLDEP-NEXT: ret
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%res = call <vscale x 2 x i32> @llvm.vector.splice(<vscale x 2 x i32> %a, <vscale x 2 x i32> undef, i32 3)
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ret <vscale x 2 x i32> %res
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}
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define <vscale x 2 x i32> @splice_nxv2i32_slideup_undef(<vscale x 2 x i32> %a) #0 {
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; CHECK-LABEL: splice_nxv2i32_slideup_undef:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
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; CHECK-NEXT: vslideup.vi v9, v8, 3
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; CHECK-NEXT: vmv.v.v v8, v9
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; CHECK-NEXT: ret
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%res = call <vscale x 2 x i32> @llvm.vector.splice(<vscale x 2 x i32> undef, <vscale x 2 x i32> %a, i32 -3)
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ret <vscale x 2 x i32> %res
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}
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attributes #0 = { vscale_range(2,0) }

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