How to model ADC/DAC

[jankap]

Is it already possible to model ideal and non-ideal analog-digital-converters (ADC) or DACs given the parts in the standard library?

Thanks :)

[baggepinnen]

Not quite :/

We are currently lacking

• IntegerOutput (DigitalOutput). However, we do now support variables with integer type, so such an output connector could be implemented.
• Handling the trigger condition could be done with an event, but events are currently known to have a number of bugs. If the triggering is periodic, it could in principle be implemented as a clocked system, unfortunately, support for this is not complete yet so this alternative is not yet available.