add back needed files

Author: mattvenn

src/Makefile

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+# Makefile
+# See https://docs.cocotb.org/en/stable/quickstart.html for more info
+
+# defaults
+SIM ?= icarus
+TOPLEVEL_LANG ?= verilog
+
+VERILOG_SOURCES += $(PWD)/tb.v $(PWD)/counter.v $(PWD)/decoder.v
+
+# TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file
+TOPLEVEL = tb
+
+# MODULE is the basename of the Python test file
+MODULE = test
+
+# include cocotb's make rules to take care of the simulator setup
+include $(shell cocotb-config --makefiles)/Makefile.sim
+

src/counter.v

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+`default_nettype none
+
+module seven_segment_seconds #( parameter MAX_COUNT = 1000 ) (
+  input [7:0] io_in,
+  output [7:0] io_out
+);
+    
+    wire clk = io_in[0];
+    wire reset = io_in[1];
+    wire [6:0] led_out;
+    assign io_out[6:0] = led_out;
+
+    // external clock is 1000Hz, so need 10 bit counter
+    reg [9:0] second_counter;
+    reg [3:0] digit;
+
+    always @(posedge clk) begin
+        // if reset, set counter to 0
+        if (reset) begin
+            second_counter <= 0;
+            digit <= 0;
+        end else begin
+            // if up to 16e6
+            if (second_counter == MAX_COUNT) begin
+                // reset
+                second_counter <= 0;
+
+                // increment digit
+                digit <= digit + 1'b1;
+
+                // only count from 0 to 9
+                if (digit == 9)
+                    digit <= 0;
+
+            end else
+                // increment counter
+                second_counter <= second_counter + 1'b1;
+        end
+    end
+
+    // instantiate segment display
+    seg7 seg7(.counter(digit), .segments(led_out));
+
+endmodule

src/decoder.v

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+
+/*
+      -- 1 --
+     |       |
+     6       2
+     |       |
+      -- 7 --
+     |       |
+     5       3
+     |       |
+      -- 4 --
+*/
+
+module seg7 (
+    input wire [3:0] counter,
+    output reg [6:0] segments
+);
+
+    always @(*) begin
+        case(counter)
+            //                7654321
+            0:  segments = 7'b0111111;
+            1:  segments = 7'b0000110;
+            2:  segments = 7'b1011011;
+            3:  segments = 7'b1001111;
+            4:  segments = 7'b1100110;
+            5:  segments = 7'b1101101;
+            6:  segments = 7'b1111100;
+            7:  segments = 7'b0000111;
+            8:  segments = 7'b1111111;
+            9:  segments = 7'b1100111;
+            default:    
+                segments = 7'b0000000;
+        endcase
+    end
+
+endmodule
+

src/tb.gtkw

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+[*]
+[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
+[*] Thu Oct 27 10:17:53 2022
+[*]
+[dumpfile] "/home/matt/work/asic-workshop/shuttle7/tt02-submission-template/src/tb.vcd"
+[dumpfile_mtime] "Thu Oct 27 10:17:11 2022"
+[dumpfile_size] 14468
+[savefile] "/home/matt/work/asic-workshop/shuttle7/tt02-submission-template/src/tb.gtkw"
+[timestart] 0
+[size] 2286 698
+[pos] -1 -1
+*-30.600000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] tb.
+[sst_width] 343
+[signals_width] 264
+[sst_expanded] 1
+[sst_vpaned_height] 190
+@28
+tb.clk
+@29
+tb.rst
+@22
+tb.segments[6:0]
+[pattern_trace] 1
+[pattern_trace] 0