diff --git a/vunit/source_file.py b/vunit/source_file.py
index 289d68f41..7393a2c43 100644
--- a/vunit/source_file.py
+++ b/vunit/source_file.py
@@ -348,7 +348,7 @@ def add_to_library(self, library):
 # lower case representation of supported extensions
 VHDL_EXTENSIONS = (".vhd", ".vhdl", ".vho")
 VERILOG_EXTENSIONS = (".v", ".vp", ".vams", ".vo")
-SYSTEM_VERILOG_EXTENSIONS = (".sv",)
+SYSTEM_VERILOG_EXTENSIONS = (".sv", ".svp")
 VERILOG_FILE_TYPES = ("verilog", "systemverilog")
 FILE_TYPES = ("vhdl",) + VERILOG_FILE_TYPES