diff --git a/tests/unit/test_vhdl_parser.py b/tests/unit/test_vhdl_parser.py
index fd8a50518..478b198c9 100644
--- a/tests/unit/test_vhdl_parser.py
+++ b/tests/unit/test_vhdl_parser.py
@@ -568,15 +568,27 @@ def test_getting_component_instantiations_from_design_file(self):
 
     label3Foo : foo3 port map (clk, rst, X"A");
 
+    label4Foo : foo4
+        generic map (
+            g_POWER  => 2 ** 10,
+            g_DIVIDE => 10 / 5
+        )
+        port map(
+            clk => '1',
+            rst => '0',
+            output => "00"
+        ) ;
+
 end architecture;
 
 """
         )
         component_instantiations = design_file.component_instantiations
-        self.assertEqual(len(component_instantiations), 3)
+        self.assertEqual(len(component_instantiations), 4)
         self.assertEqual(component_instantiations[0], "foo")
         self.assertEqual(component_instantiations[1], "foo2")
         self.assertEqual(component_instantiations[2], "foo3")
+        self.assertEqual(component_instantiations[3], "foo4")
 
     def test_adding_generics_to_entity(self):
         entity = VHDLEntity("name")
diff --git a/vunit/vhdl_parser.py b/vunit/vhdl_parser.py
index 71a58b469..494db177b 100644
--- a/vunit/vhdl_parser.py
+++ b/vunit/vhdl_parser.py
@@ -85,9 +85,16 @@ def parse(cls, code):
         )
 
     _component_re = re.compile(
-        r"[a-zA-Z]\w*\s*\:\s*(?:component)?\s*(?:(?:[a-zA-Z]\w*)\.)?([a-zA-Z]\w*)\s*"
-        r"(?:generic|port) map\s*\([\s\w\=\>\,\.\)\(\+\-\'\"]*\);",
-        re.IGNORECASE,
+        r"""
+        [a-zA-Z]\w*               # Label
+        \s*\:\s*                  # Semicolon
+        (?:component)?\s*         # Optional component keyword
+        (?:(?:[a-zA-Z]\w*)\.)?    # Optional library name
+        ([a-zA-Z]\w*)\s*          # Capture component name
+        (?:generic|port)\s+map\s* # Generic/port map
+        \([\s\w\=\>\,\.\)\(\+\-\'\"\*\/]*\)
+        """,
+        re.MULTILINE | re.IGNORECASE | re.VERBOSE | re.DOTALL,
     )