diff --git a/test/src/com/xilinx/rapidwright/design/TestCell.java b/test/src/com/xilinx/rapidwright/design/TestCell.java
index 2594de7a9..7a62264aa 100644
--- a/test/src/com/xilinx/rapidwright/design/TestCell.java
+++ b/test/src/com/xilinx/rapidwright/design/TestCell.java
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2022, Xilinx, Inc.
- * Copyright (c) 2022-2023, Advanced Micro Devices, Inc.
+ * Copyright (c) 2022-2024, Advanced Micro Devices, Inc.
  * All rights reserved.
  *
  * Author: Eddie Hung, Xilinx Research Labs.
@@ -24,6 +24,7 @@
 package com.xilinx.rapidwright.design;
 
 
+import com.xilinx.rapidwright.device.BELPin;
 import com.xilinx.rapidwright.device.Device;
 import com.xilinx.rapidwright.support.RapidWrightDCP;
 import com.xilinx.rapidwright.util.FileTools;
@@ -32,7 +33,9 @@
 import org.junit.jupiter.api.Test;
 import org.junit.jupiter.params.ParameterizedTest;
 import org.junit.jupiter.params.provider.CsvSource;
+import org.junit.jupiter.params.provider.ValueSource;
 
+import java.util.Arrays;
 import java.util.List;
 
 public class TestCell {
@@ -110,4 +113,38 @@ public void testFFRoutethruCell() {
             Assertions.assertEquals(0, VivadoTools.reportRouteStatus(d).netsWithRoutingErrors);
         }
     }
+
+    @ParameterizedTest
+    @ValueSource(booleans = {true, false})
+    void testGetSitePinFromLogicalPin(boolean createAX) {
+        Design design = new Design("top", Device.PYNQ_Z1);
+        SiteInst si = design.createSiteInst("SLICE_X1Y0");
+        Net net = design.createNet("net");
+        SitePinInst A3 = net.createPin("A3", si);
+        SitePinInst AX = (createAX) ? net.createPin("AX", si) : null;
+
+        Cell ff = design.createAndPlaceCell("ff", Unisim.FDRE, "SLICE_X1Y0/AFF");
+
+        BELPin ffD = ff.getBEL().getPin("D");
+        for (SitePinInst spi : Arrays.asList(AX, A3)) {
+            if (spi == null)
+                continue;
+
+            Assertions.assertNull(DesignTools.getRoutedSitePin(ff, net, "D"));
+            if (createAX) {
+                // FIXME: Known broken -- see https://github.com/Xilinx/RapidWright/issues/473
+                Assertions.assertEquals("IN SLICE_X1Y0.AX", ff.getSitePinFromLogicalPin("D", null).toString());
+            } else {
+                Assertions.assertNull(ff.getSitePinFromLogicalPin("D", null));
+            }
+
+            BELPin bp = spi.getBELPin();
+            Assertions.assertTrue(si.routeIntraSiteNet(net, bp, ffD));
+
+            Assertions.assertEquals(bp.getName(), DesignTools.getRoutedSitePin(ff, net, "D"));
+            Assertions.assertEquals(spi, ff.getSitePinFromLogicalPin("D", null));
+
+            Assertions.assertTrue(si.unrouteIntraSiteNet(bp, ffD));
+        }
+    }
 }