Parsing verilog design for circuit path

[jiahzhang]

Is there a straightforward way of parsing the design for an arbitrary flop-to-flop gate order? I saw torder seems to print everything, which I don't want.

[KrystalDelusion]

You can use %ci* and %co* to get the input and output cones respectively, and find the intersection with %i. e.g. you have some flop top/dff1 and another top/dff2; select top/dff1 %co* top/dff2 %ci* %i will select everything in the output cone of top/dff1 and everything in the input cone of top/dff2, then take the intersection giving just the elements in between. If you want them in topological order you should be able to call torder with that selection statement, i.e. torder top/dff1 %co* top/dff2 %ci* %i.

[jiahzhang]

It seems like %co:* and %ci:* potentially intersect over the whole design. How do I restrain it to stop at its first flop?

[KrystalDelusion]

There's some documentation you can have a look at: https://yosyshq.readthedocs.io/projects/yosys/en/latest/using_yosys/more_scripting/selections.html#advanced-logic-cone-selection

I think it would be something like select top/dff1 %co %co*:-$dff. %co*:-$dff gives the whole output cone, without following any of the $dff cells. So you have to run a single %co beforehand to get the immediate outputs, and then you're following the output cones of those. If your flops aren't $dff cells you'll need to adjust the expression.

[KrystalDelusion]

Alternatively, you can give a number to the %co instead of *, i.e. %co4 will step through the outputs 4 times. * there means "until you can't extend further".