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library: jesd204: ad_ip_jesd204_tpl_adc: Add optional pipeline stage inside deframer
Signed-off-by: Bogdan Luncan <[email protected]>
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5 files changed

+45
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‎library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.v

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// ***************************************************************************
22
// ***************************************************************************
3-
// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved.
3+
// Copyright (C) 2018-2023, 2025 Analog Devices, Inc. All rights reserved.
44
//
55
// In this HDL repository, there are many different and unique modules, consisting
66
// of various HDL (Verilog or VHDL) components. The individual modules are
@@ -52,7 +52,8 @@ module ad_ip_jesd204_tpl_adc #(
5252
parameter TWOS_COMPLEMENT = 1,
5353
parameter EXT_SYNC = 0,
5454
parameter PN7_ENABLE = 1,
55-
parameter PN15_ENABLE = 1
55+
parameter PN15_ENABLE = 1,
56+
parameter NUM_PIPELINE_STAGES = 0
5657
) (
5758

5859
// jesd interface
@@ -209,7 +210,8 @@ module ad_ip_jesd204_tpl_adc #(
209210
.DMA_BITS_PER_SAMPLE (DMA_BITS_PER_SAMPLE),
210211
.EXT_SYNC (EXT_SYNC),
211212
.PN7_ENABLE (PN7_ENABLE),
212-
.PN15_ENABLE(PN15_ENABLE)
213+
.PN15_ENABLE(PN15_ENABLE),
214+
.NUM_PIPELINE_STAGES (NUM_PIPELINE_STAGES)
213215
) i_core (
214216
.clk (link_clk),
215217

‎library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_core.v

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// ***************************************************************************
22
// ***************************************************************************
3-
// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved.
3+
// Copyright (C) 2018-2023, 2025 Analog Devices, Inc. All rights reserved.
44
//
55
// In this HDL repository, there are many different and unique modules, consisting
66
// of various HDL (Verilog or VHDL) components. The individual modules are
@@ -50,7 +50,8 @@ module ad_ip_jesd204_tpl_adc_core #(
5050
parameter TWOS_COMPLEMENT = 1,
5151
parameter EXT_SYNC = 0,
5252
parameter PN7_ENABLE = 1,
53-
parameter PN15_ENABLE = 1
53+
parameter PN15_ENABLE = 1,
54+
parameter NUM_PIPELINE_STAGES = 0
5455
) (
5556
input clk,
5657

@@ -119,7 +120,8 @@ module ad_ip_jesd204_tpl_adc_core #(
119120
.OCTETS_PER_BEAT (OCTETS_PER_BEAT),
120121
.EN_FRAME_ALIGN (EN_FRAME_ALIGN),
121122
.LINK_DATA_WIDTH (LINK_DATA_WIDTH),
122-
.ADC_DATA_WIDTH (ADC_DATA_WIDTH)
123+
.ADC_DATA_WIDTH (ADC_DATA_WIDTH),
124+
.NUM_PIPELINE_STAGES (NUM_PIPELINE_STAGES)
123125
) i_deframer (
124126
.clk (clk),
125127
.link_sof (link_sof),

‎library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_deframer.v

Lines changed: 25 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// ***************************************************************************
22
// ***************************************************************************
3-
// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved.
3+
// Copyright (C) 2018-2023, 2025 Analog Devices, Inc. All rights reserved.
44
//
55
// In this HDL repository, there are many different and unique modules, consisting
66
// of various HDL (Verilog or VHDL) components. The individual modules are
@@ -43,6 +43,7 @@ module ad_ip_jesd204_tpl_adc_deframer #(
4343
parameter SAMPLES_PER_FRAME = 1,
4444
parameter OCTETS_PER_BEAT = 8,
4545
parameter EN_FRAME_ALIGN = 0,
46+
parameter NUM_PIPELINE_STAGES = 0,
4647
parameter LINK_DATA_WIDTH = OCTETS_PER_BEAT * 8 * NUM_LANES,
4748
parameter ADC_DATA_WIDTH = LINK_DATA_WIDTH * CONVERTER_RESOLUTION / BITS_PER_SAMPLE
4849
) (
@@ -65,19 +66,39 @@ module ad_ip_jesd204_tpl_adc_deframer #(
6566
NUM_CHANNELS / NUM_LANES;
6667
localparam FRAMES_PER_BEAT = OCTETS_PER_BEAT * 8 / BITS_PER_LANE_PER_FRAME;
6768

69+
wire [LINK_DATA_WIDTH-1:0] link_data_r;
70+
wire [LINK_DATA_WIDTH-1:0] frame_data_r;
71+
wire [LINK_DATA_WIDTH-1:0] adc_data_r;
72+
6873
wire [LINK_DATA_WIDTH-1:0] link_data_s;
6974
wire [LINK_DATA_WIDTH-1:0] link_data_msb_s;
7075
wire [LINK_DATA_WIDTH-1:0] frame_data_s;
7176
wire [LINK_DATA_WIDTH-1:0] adc_data_msb;
7277

78+
util_pipeline_stage #(
79+
.REGISTERED (NUM_PIPELINE_STAGES),
80+
.WIDTH (3*LINK_DATA_WIDTH)
81+
) i_pipeline_stages (
82+
.clk (clk),
83+
.in ({
84+
link_data_s,
85+
frame_data_s,
86+
adc_data_msb
87+
}),
88+
.out ({
89+
link_data_r,
90+
frame_data_r,
91+
adc_data_r
92+
}));
93+
7394
// data multiplex
7495

7596
genvar i;
7697
genvar j;
7798
generate
7899
/* Reorder octets MSB first */
79100
for (i = 0; i < LINK_DATA_WIDTH; i = i + 8) begin: g_adc_data
80-
assign link_data_msb_s[i+:8] = link_data_s[LINK_DATA_WIDTH-1-i-:8];
101+
assign link_data_msb_s[i+:8] = link_data_r[LINK_DATA_WIDTH-1-i-:8];
81102
end
82103

83104
/* Slice lanes into frames */
@@ -95,7 +116,7 @@ module ad_ip_jesd204_tpl_adc_deframer #(
95116
.WORDS_PER_GROUP (NUM_CHANNELS),
96117
.WORD_WIDTH (BITS_PER_CHANNEL_PER_FRAME)
97118
) i_frames_to_channels (
98-
.data_in (frame_data_s),
119+
.data_in (frame_data_r),
99120
.data_out (adc_data_msb));
100121

101122
/* Reorder samples LSB first and remove tail bits */
@@ -105,7 +126,7 @@ module ad_ip_jesd204_tpl_adc_deframer #(
105126
localparam src_msb = LINK_DATA_WIDTH - 1 - i * src_w ;
106127
localparam dst_lsb = i * dst_w;
107128

108-
assign adc_data[dst_lsb+:dst_w] = adc_data_msb[src_msb-:dst_w];
129+
assign adc_data[dst_lsb+:dst_w] = adc_data_r[src_msb-:dst_w];
109130
end
110131
endgenerate
111132

‎library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_hw.tcl

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
###############################################################################
2-
## Copyright (C) 2018-2022, 2024 Analog Devices, Inc. All rights reserved.
2+
## Copyright (C) 2018-2022, 2024-2025 Analog Devices, Inc. All rights reserved.
33
### SPDX short identifier: ADIJESD204
44
###############################################################################
55

@@ -50,6 +50,12 @@ ad_ip_parameter OCTETS_PER_BEAT INTEGER 4 true [list \
5050
GROUP $group \
5151
]
5252

53+
ad_ip_parameter NUM_PIPELINE_STAGES INTEGER 0 true [list \
54+
DISPLAY_NAME "Number of pipeline stages inside the deframer" \
55+
ALLOWED_RANGES {0 1 2} \
56+
GROUP $group \
57+
]
58+
5359
set group "JESD204 Deframer Configuration"
5460

5561
ad_ip_parameter NUM_LANES INTEGER 1 true [list \

‎library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_ip.tcl

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
###############################################################################
2-
## Copyright (C) 2018-2022 Analog Devices, Inc. All rights reserved.
2+
## Copyright (C) 2018-2022, 2025 Analog Devices, Inc. All rights reserved.
33
### SPDX short identifier: ADIJESD204
44
###############################################################################
55

@@ -21,6 +21,7 @@ adi_ip_files ad_ip_jesd204_tpl_adc [list \
2121
"$ad_hdl_dir/library/common/up_adc_channel.v" \
2222
"$ad_hdl_dir/library/common/util_ext_sync.v" \
2323
"$ad_hdl_dir/library/common/ad_xcvr_rx_if.v" \
24+
"$ad_hdl_dir/library/common/util_pipeline_stage.v" \
2425
"$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
2526
"$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
2627
"$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \
@@ -68,6 +69,7 @@ foreach {p v} {
6869
"CONVERTER_RESOLUTION" "8 11 12 14 16" \
6970
"SAMPLES_PER_FRAME" "1 2 3 4 6 8 12 16" \
7071
"OCTETS_PER_BEAT" "4 6 8 12 16 32 64" \
72+
"NUM_PIPELINE_STAGES" "0 1 2" \
7173
} { \
7274
set_property -dict [list \
7375
"value_validation_type" "list" \

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