library: jesd204: tb: Make tb work with modelsim

Signed-off-by: bluncan <[email protected]>

Author: bluncan

library/jesd204/tb/sim_jesd204_fec

@@ -0,0 +1,48 @@
+#!/bin/bash
+
+export SIMULATOR=modelsim
+
+SOURCE="tb_jesd204_fec.sv"
+SOURCE+=" ../../util_cdc/sync_bits.v"
+SOURCE+=" ../../util_cdc/sync_event.v"
+SOURCE+=" ../../common/ad_mem_dist.v"
+SOURCE+=" ../../common/util_pipeline_stage.v"
+
+SOURCE+=" ../jesd204_common/jesd204_lmfc.v"
+SOURCE+=" ../jesd204_common/jesd204_scrambler.v"
+SOURCE+=" ../jesd204_common/jesd204_scrambler_64b.v"
+SOURCE+=" ../jesd204_common/jesd204_crc12.v"
+SOURCE+=" ../jesd204_common/jesd204_frame_mark.v"
+SOURCE+=" ../jesd204_common/jesd204_frame_align_replace.v"
+
+SOURCE+=" ../jesd204_common/lfsr_input.sv"
+SOURCE+=" ../jesd204_tx/jesd204_fec_encode.sv"
+SOURCE+=" ../jesd204_tx/jesd204_tx_lane.v"
+SOURCE+=" ../jesd204_tx/jesd204_tx_lane_64b.v"
+SOURCE+=" ../jesd204_tx/jesd204_tx_gearbox.v"
+SOURCE+=" ../jesd204_tx/jesd204_tx_header.v"
+SOURCE+=" ../jesd204_tx/jesd204_tx_ctrl.v"
+SOURCE+=" ../jesd204_tx/jesd204_tx.v"
+
+SOURCE+=" ../jesd204_rx/jesd204_rx_fec_lfsr.sv"
+SOURCE+=" ../jesd204_rx/jesd204_fec_decode.sv"
+SOURCE+=" ../jesd204_rx/jesd204_rx_lane.v"
+SOURCE+=" ../jesd204_rx/jesd204_rx_lane_64b.v"
+SOURCE+=" ../jesd204_rx/jesd204_rx_header.v"
+SOURCE+=" ../jesd204_rx/jesd204_rx_cgs.v"
+SOURCE+=" ../jesd204_rx/jesd204_rx_ctrl.v"
+SOURCE+=" ../jesd204_rx/jesd204_rx_ctrl_64b.v"
+SOURCE+=" ../jesd204_rx/elastic_buffer.v"
+SOURCE+=" ../jesd204_rx/error_monitor.v"
+SOURCE+=" ../jesd204_rx/jesd204_ilas_monitor.v"
+SOURCE+=" ../jesd204_rx/align_mux.v"
+SOURCE+=" ../jesd204_rx/jesd204_lane_latency_monitor.v"
+SOURCE+=" ../jesd204_rx/jesd204_rx_frame_align.v"
+SOURCE+=" ../jesd204_rx/jesd204_rx.v"
+
+SOURCE+=" ../jesd204_rx_static_config/jesd204_rx_static_config.v"
+SOURCE+=" ../jesd204_tx_static_config/jesd204_tx_static_config.v"
+SOURCE+=" ../jesd204_tx_static_config/jesd204_ilas_cfg_static.v"
+
+cd `dirname $0`
+source ../../common/tb/run_tb.sh

library/jesd204/tb/tb_jesd204_fec

@@ -24,13 +24,15 @@ module tb_jesd204_fec;
   localparam ERROR_BITS =  64'h1FF000; // Bits of decoder input data to corrupt
   localparam FEC_ERROR_BITS = '0; // {1'b1, 25'b0};
 
+  parameter VCD_FILE = {"tb_jesd204_fec.vcd"};
+  `include "tb_base.v"
+
   logic [INPUT_DATA_WIDTH-1:0]    DATA_VALUE_REVERSED;
   logic [INPUT_DATA_WIDTH-1:0]    data;
 
   logic [FEC_WIDTH-1:0]           fec;
   logic [FEC_WIDTH-1:0]           fec_saved;
   logic [FEC_WIDTH-1:0]           decode_fec_in;
-  reg                             clk = 1'b0;
   logic                           rst;
   logic                           fec_in_valid;
   logic                           shift_en;

library/jesd204/tb/tb_jesd204_fec.sv

@@ -18,11 +18,13 @@ module tb_jesd204_fec_encode;
   localparam INPUT_DATA_WIDTH = 2048;
   localparam logic [INPUT_DATA_WIDTH-1:0] DATA_VALUE = {1'b1, 2047'b0};
 
+  parameter VCD_FILE = {"tb_jesd204_fec_encode.vcd"};
+  `include "tb_base.v"
+
   logic [INPUT_DATA_WIDTH-1:0]    DATA_VALUE_REVERSED;
   logic [DATA_WIDTH-1:0]          data;
 
   logic [FEC_WIDTH-1:0]           fec;
-  reg                             clk = 1'b0;
   logic                           rst;
   logic                           shift_en;
   logic [DATA_WIDTH-1:0]          data_in;

library/jesd204/tb/sim_jesd204_fec_encode renamed to library/jesd204/tb/tb_jesd204_fec_encode

@@ -9,12 +9,14 @@
 `default_nettype none
 
 module tb_lfsr_input;
-
   localparam LFSR_WIDTH = 26;
   localparam [LFSR_WIDTH:1] RESET_VAL = {LFSR_WIDTH{1'b0}};
   localparam [LFSR_WIDTH:1] LFSR_POLYNOMIAL = 26'h2210110;
   localparam MAX_SHIFT_CNT = 64;
 
+  parameter VCD_FILE = {"tb_lfsr_input.vcd"};
+  `include "tb_base.v"
+
   // localparam INPUT_DATA_WIDTH = 64;
   // localparam logic [INPUT_DATA_WIDTH-1:0] DATA_VALUE = 64'h8001020305050423;
   localparam INPUT_DATA_WIDTH = 2048;
@@ -25,7 +27,6 @@ module tb_lfsr_input;
 
   logic [MAX_SHIFT_CNT-1:0]           data_out;
   logic [LFSR_WIDTH:1]                shift_reg;
-  reg                                 clk = 1'b0;
   logic                               rst;
   logic                               shift_en;
   logic [$clog2(MAX_SHIFT_CNT)-1:0]   shift_cnt;

library/jesd204/tb/tb_jesd204_fec_encode.sv

@@ -10,7 +10,6 @@
 `default_nettype none
 
 module tb_link_layer_fec;
-
   localparam NUM_LANES=2;
   localparam NUM_LINKS=1;
   localparam SCR = 0;
@@ -29,8 +28,9 @@ module tb_link_layer_fec;
   // localparam NEXT_ERROR_BITS = 64'h0000000000000000;
   localparam REPORT_GOOD_DATA = 1'b1;
 
-  reg                             clk = 1'b0;
-  reg                             sysref = 1'b0;
+  parameter VCD_FILE = {"tb_link_layer_fec.vcd"};
+  `include "tb_base.v"
+
   logic                           rst;
   logic [INPUT_DATA_WIDTH-1:0]    DATA_VALUE_REVERSED;
   logic [INPUT_DATA_WIDTH-1:0]    data;
@@ -238,6 +238,7 @@ module tb_link_layer_fec;
         cur_tx_data = tx_data_q.pop_front();
         if(cur_tx_data !== rx_data) begin
           $error("RX Cycle: %d Data mismatch. Expected: %X  Observed: %X", rx_cycle_cnt, cur_tx_data, rx_data);
+          failed = 1'b1;
         end else if(REPORT_GOOD_DATA) begin
           $display("RX Cycle: %d Good data:%X", rx_cycle_cnt, cur_tx_data);
         end