library/spi_engine: fix corner case in the execution

Inserts a ready signal for when the valid_indices
has finished its inner logic. This avoid the possible
issue where the latency of the command is smaller than
this logic.

This could only happen in the FIFO mode.

Signed-off-by: Carlos Souza <[email protected]>

Author: caosjr

library/spi_engine/spi_engine_execution/spi_engine_execution_shiftreg.v

@@ -93,6 +93,7 @@ module spi_engine_execution_shiftreg #(
   wire sdo_toshiftreg; //it is using the valid data for shifting in this cycle
   wire last_sdi_bit;
   wire trigger_rx_s;
+  wire index_ready;
   wire sdo_data_ready_int;
 
   // sdo_data_ready_int is active when two conditions are true:
@@ -102,7 +103,7 @@ module spi_engine_execution_shiftreg #(
   //    (s_offload_active || current_instr == CMD_TRANSFER)
   //      when s_offload_active, it is possible to prefetch
   //      when !s_offload_active, it is waiting for write instruction
-  assign sdo_data_ready_int = ((!data_sdo_v) || (sdo_toshiftreg)) && (s_offload_active || exec_cmd);
+  assign sdo_data_ready_int = ((!data_sdo_v) || (sdo_toshiftreg)) && (s_offload_active || (exec_cmd & index_ready));
   assign sdo_data_ready = sdo_data_ready_int;
   assign sdo_io_ready = data_sdo_v;
 
@@ -126,7 +127,8 @@ module spi_engine_execution_shiftreg #(
     .transfer_active (transfer_active),
     .trigger_tx (trigger_tx),
     .first_bit (first_bit),
-    .sdo_enabled(sdo_enabled),
+    .sdo_enabled (sdo_enabled),
+    .index_ready (index_ready),
     .data_assembled (aligned_sdo_data),
     .last_handshake (data_sdo_v));
 

library/spi_engine/spi_engine_execution/spi_engine_execution_shiftreg_data_assemble.v

@@ -56,6 +56,7 @@ module spi_engine_execution_shiftreg_data_assemble #(
   input                                   trigger_tx,
   input                                   first_bit,
   input                                   sdo_enabled,
+  output                                  index_ready,
   output [(NUM_OF_SDIO * DATA_WIDTH)-1:0] data_assembled,
   output                                  last_handshake
 );
@@ -79,6 +80,7 @@ module spi_engine_execution_shiftreg_data_assemble #(
 
   assign data_assembled = aligned_data;
   assign last_handshake = last_handshake_int;
+  assign index_ready    = index_ready_reg;
 
   // register data
   always @(posedge clk) begin
@@ -107,16 +109,19 @@ module spi_engine_execution_shiftreg_data_assemble #(
   reg [3:0] i;
   reg [3:0] j;
   reg [3:0] mask_index;
+  reg       index_ready_reg;
   always @(posedge clk) begin
     if (resetn == 1'b0) begin
       num_active_lanes <= NUM_OF_SDIO;
+      index_ready_reg <= 1'b0;
       mask_index <= 0;
       j <= 0;
     end else begin
       if (exec_sdo_lane_cmd) begin
         count_active_lanes = 0;
         i = 0;
         j <= 0;
+        index_ready_reg <= 1'b0;
         mask_index <= 0;
         for (i = 0; i < NUM_OF_SDIO; i = i + 1) begin
           count_active_lanes = count_active_lanes + current_cmd[i];
@@ -129,6 +134,7 @@ module spi_engine_execution_shiftreg_data_assemble #(
             mask_index <= mask_index + 1;
           end
           j <= j + 1;
+          index_ready_reg <= (j == NUM_OF_SDIO-1) ? 1'b1 : 1'b0;
         end
       end
     end