diff --git a/docs/library/spi_engine/axi_spi_engine.rst b/docs/library/spi_engine/axi_spi_engine.rst index aa219216312..57d666132ed 100644 --- a/docs/library/spi_engine/axi_spi_engine.rst +++ b/docs/library/spi_engine/axi_spi_engine.rst @@ -116,8 +116,18 @@ If an application attempts to read data while the FIFO is empty undefined data is returned and the state of the FIFO remains unmodified. It is possible to read the first entry in the SDI FIFO without removing it by reading from the SDI_FIFO_PEEK register. +It is important to point out that each read represents one active lane of the SPI. +So, for ``N`` active lanes it is necessary to read ``N`` times. Reading +always starts from lane 0. The number of valid entries in the SDI FIFO register can be queried by reading -the SDI_FIFO_LEVEL register. +the SDI_FIFO_LEVEL register. This value must be a multiple of ``NUM_OF_SDIO``. + +Data can be inserted into the SDO FIFO by writing to the SDO_FIFO register +**only the valid lanes**. For example, if there are 4 lanes and just 2 of them +are enabled, then the programmer must write 2 values to this register. The +remaining lanes will contain ``SDO_DEFAULT`` value defined in +:ref:`spi_engine execution`. The number of valid lanes are defined in +:ref:`spi_engine configuration-registers`. If the peripheral is disabled by setting the ENABLE register to 0 any data stored in the FIFOs is discarded and the state of the FIFO is reset. diff --git a/docs/library/spi_engine/control-interface.rst b/docs/library/spi_engine/control-interface.rst index 384e140c139..c04b76e8c7a 100644 --- a/docs/library/spi_engine/control-interface.rst +++ b/docs/library/spi_engine/control-interface.rst @@ -76,7 +76,7 @@ Signal Pins - ``sdi_valid`` - Input - Valid signal of the SDI stream - * - [(NUM_OF_SDI*DATA_WIDTH-1):0] + * - [(NUM_OF_SDIO*DATA_WIDTH-1):0] - ``sdi_data`` - Input - Data signal of the SDI stream diff --git a/docs/library/spi_engine/instruction-format.rst b/docs/library/spi_engine/instruction-format.rst index 11aec5b2112..dca9fb8afc7 100644 --- a/docs/library/spi_engine/instruction-format.rst +++ b/docs/library/spi_engine/instruction-format.rst @@ -3,8 +3,9 @@ SPI Engine Instruction Set Specification ================================================================================ -The SPI Engine instruction set is a simple 16-bit instruction set of which -13-bits are currently allocated (bits 15,11,10 are always 0). +The SPI Engine instruction set is a 16-bit instruction set of which 13-bits are +currently allocated (bits 15 and 11 are always 0). Bit 10 is only being used by +the :ref:`spi_engine write-configuration-instruction`. Instructions -------------------------------------------------------------------------------- @@ -12,22 +13,51 @@ Instructions Transfer Instruction ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -== == == == == == = = = = = = = = = = -15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -== == == == == == = = = = = = = = = = -0 0 0 0 0 0 r w n n n n n n n n -== == == == == == = = = = = = = = = = - -The transfer instructions perform a low-level SPI transfer. It will generate -SCLK transitions for the specified amount of cycles according to the SPI -configuration register. If the r bit is set the SDI pin will be sampled and -stored in the shift register at the end of each word the data is output on the -SDI_DATA stream. If the w bit is set the SDO pin will be updated with the data -received from the SDO_DATA stream. If the w bit is set the sdo_t signal will -also be set to 0 for the duration of the transfer. If the SDI_DATA stream is not -able to accept data or the SDO_DATA stream is not able to provide data the -execution is stalled at the end/start of the transfer until data is -accepted/becomes available. +.. list-table:: + :header-rows: 1 + + * - 15 + - 14 + - 13 + - 12 + - 11 + - 10 + - 9 + - 8 + - 7 + - 6 + - 5 + - 4 + - 3 + - 2 + - 1 + - 0 + * - rv + - 0 + - 0 + - 0 + - rv + - rv + - r + - w + - n + - n + - n + - n + - n + - n + - n + - n + +The transfer instruction perform a low-level SPI transfer. It generates SCLK +transitions for the specified amount of cycles according to the SPI +configuration register. If the r bit is set, the SDI pin is sampled and stored +in the shift register up to the end of the word, and then is output in the +SDI_DATA stream. If the w bit is set, the SDO pin is updated with the data +received from the SDO_DATA stream. By setting w bit, the sdo_t pin is set to 0 +during the transfer. If the SDI_DATA stream cannot accept any data or SDO_DATA +stream cannot provide any data, then the execution module is stalled until +there's no longer any backpressure condition. .. list-table:: :widths: 10 15 75 @@ -36,17 +66,20 @@ accepted/becomes available. * - Bits - Name - Description + * - rv + - Reserved + - Reserved bit. Must always be set to 0. * - r - Read - - If set to 1 data will be read from the SDI pin during and the read words - will be available on the SDI_DATA interface. + - If set to 1, data is read from the SDI pin and the read words are + available on the SDI_DATA interface. * - w - Write - - If set to 1 data will be taken from the SDO_DATA interface and output on + - If set to 1, data is consumed from the SDO_DATA interface and output on the SDO pin. * - n - Length - - n + 1 number of words that will be transferred. + - n + 1 number of words to be transferred. .. _spi_engine cs-instruction: @@ -54,29 +87,59 @@ accepted/becomes available. Chip-Select Instruction ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -== == == == == == = = = = = = = = = = -15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -== == == == == == = = = = = = = = = = -0 0 0 1 0 0 t t s s s s s s s s -== == == == == == = = = = = = = = = = - -The chip-select instruction updates the value chip-select output signal of the -SPI Engine execution module. - -The physical outputs on each pin may be inverted relative to the command -according to the mask set by :ref:`spi_engine cs-invert-mask-instruction`. The -Invert Mask acts only on the output registers of the Chip-Select pins. Thus, if -the last 8 bits of the Chip-Select instruction are 0xFE, only CS[0] will be -active regardless of polarity. The polarity inversion process (if needed) is -transparent to the programmer. - -Before and after the update is performed the execution module is paused for the -specified delay. The length of the delay depends on the module clock frequency, -the setting of the prescaler register and the parameter :math:`t` of the -instruction. This delay is inserted before and after the update of the -chip-select signal, so the total execution time of the chip-select instruction -is twice the delay, with an added fixed 2 clock cycles (fast clock, not -prescaled) before for the internal logic. +.. list-table:: + :header-rows: 1 + + * - 15 + - 14 + - 13 + - 12 + - 11 + - 10 + - 9 + - 8 + - 7 + - 6 + - 5 + - 4 + - 3 + - 2 + - 1 + - 0 + * - rv + - 0 + - 0 + - 1 + - rv + - rv + - t + - t + - s + - s + - s + - s + - s + - s + - s + - s + +The chip-select instruction updates the value of the chip-select output signal +of the SPI Engine execution module. + +The physical output value for every pin may differ from what is defined in this +instruction depending on the mask set in the +:ref:`spi_engine cs-invert-mask-instruction`, because this mask acts only on +the output registers of the Chip-Select pins. Thus, if the last 8 bits of the +Chip-Select instruction are 0xFE, only CS[0] is active regardless of polarity. +The polarity inversion process (if needed) is transparent to the programmer. + +Before and after any update, the execution module is paused for the specified +delay. The length of the delay depends on the module clock frequency, the +value of the prescaler register, and the parameter :math:`t` of the +instruction. This delay is inserted before and after any update of the +chip-select signal which results in twice the delay value defined. Furthermore, +it is necessary to add 2 clock cycles for the internal logic (fast clock, not +prescaled). .. math:: @@ -93,6 +156,9 @@ prescaled) before for the internal logic. * - Bits - Name - Description + * - rv + - Reserved + - Reserved bit. Must always be set to 0. * - t - Delay - Delay before and after setting the new configuration. @@ -100,18 +166,50 @@ prescaled) before for the internal logic. - Chip-select - The new chip-select configuration. +.. _spi_engine write-configuration-instruction: + Configuration Write Instruction ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -== == == == == == = = = = = = = = = = -15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -== == == == == == = = = = = = = = = = -0 0 1 0 0 0 r r v v v v v v v v -== == == == == == = = = = = = = = = = +.. list-table:: + :header-rows: 1 -The configuration writes instruction updates a -:ref:`spi_engine configuration-registers` -of the SPI Engine execution module with a new value. + * - 15 + - 14 + - 13 + - 12 + - 11 + - 10 + - 9 + - 8 + - 7 + - 6 + - 5 + - 4 + - 3 + - 2 + - 1 + - 0 + * - rv + - 0 + - 1 + - 0 + - rv + - rg + - rg + - rg + - v + - v + - v + - v + - v + - v + - v + - v + +The configuration write instruction updates the +:ref:`spi_engine configuration-registers` of the SPI Engine execution module +with a new value. .. list-table:: :widths: 10 15 75 @@ -120,12 +218,18 @@ of the SPI Engine execution module with a new value. * - Bits - Name - Description - * - r + * - rv + - Reserved + - Reserved bit. Must always be set to 0. + * - rg - Register - - Configuration register address. - 2'b00 = :ref:`spi_engine prescaler-configuration-register` - 2'b01 = :ref:`spi_engine spi-configuration-register` - 2'b10 = :ref:`spi_engine dynamic-transfer-length-register`. + - Configuration register address: + + - 3'b000 = :ref:`spi_engine prescaler-configuration-register`. + - 3'b001 = :ref:`spi_engine spi-configuration-register`. + - 3'b010 = :ref:`spi_engine dynamic-transfer-length-register`. + - 3'b011 = :ref:`spi_engine sdi-lane-mask-register`. + - 3'b100 = :ref:`spi_engine sdo-lane-mask-register`. * - v - Value - New value for the configuration register. @@ -133,17 +237,44 @@ of the SPI Engine execution module with a new value. Synchronize Instruction ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -== == == == == == = = = = = = = = = = -15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -== == == == == == = = = = = = = = = = -0 0 1 1 0 0 0 0 n n n n n n n n -== == == == == == = = = = = = = = = = +.. list-table:: + :header-rows: 1 -The synchronize instruction generates a synchronization event on the SYNC output -stream. This can be used to monitor the progress of the command stream. The -synchronize instruction is also used by the :ref:`spi_engine interconnect` -module to identify the end of a transaction and re-start the arbitration -process. + * - 15 + - 14 + - 13 + - 12 + - 11 + - 10 + - 9 + - 8 + - 7 + - 6 + - 5 + - 4 + - 3 + - 2 + - 1 + - 0 + * - rv + - 0 + - 1 + - 1 + - rv + - rv + - 0 + - 0 + - v + - v + - v + - v + - v + - v + - v + - v + +The synchronize instruction generates a synchronization event on the SYNC +output stream. This can be used to monitor the progress of the command stream. .. list-table:: :widths: 10 15 75 @@ -152,24 +283,57 @@ process. * - Bits - Name - Description - * - n + * - rv + - Reserved + - Reserved bit. Must always be set to 0. + * - v - id - Value of the generated synchronization event. Sleep Instruction ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -== == == == == == = = = = = = = = = = -15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -== == == == == == = = = = = = = = = = -0 0 1 1 0 0 0 1 t t t t t t t t -== == == == == == = = = = = = = = = = +.. list-table:: + :header-rows: 1 + + * - 15 + - 14 + - 13 + - 12 + - 11 + - 10 + - 9 + - 8 + - 7 + - 6 + - 5 + - 4 + - 3 + - 2 + - 1 + - 0 + * - rv + - 0 + - 1 + - 1 + - rv + - rv + - 0 + - 1 + - t + - t + - t + - t + - t + - t + - t + - t The sleep instruction stops the execution of the command stream for the -specified amount of time. The time is based on the external clock frequency the -configuration value of the prescaler register and the time parameter of the -instruction. A fixed delay of two clock cycles (fast, not affected by the prescaler) -is the minimum, needed by the internal logic. +specified amount of time. The sleep time relies on the external clock +frequency, the configuration value of the prescaler register, and the time +parameter of the instruction. Also, a 2 clock-cycle delay is required for +internal logic (fast clock, not prescaled). .. math:: @@ -182,38 +346,71 @@ is the minimum, needed by the internal logic. * - Bits - Name - Description + * - rv + - Reserved + - Reserved bit. Must always be set to 0. * - t - Time - - The amount of prescaler cycles to wait, minus one. + - The amount of prescaler cycles to wait minus one. .. _spi_engine cs-invert-mask-instruction: CS Invert Mask Instruction ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -== == == == == == = = = = = = = = = = -15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -== == == == == == = = = = = = = = = = -0 1 0 0 r r r r m m m m m m m m -== == == == == == = = = = = = = = = = +.. list-table:: + :header-rows: 1 -The CS Invert Mask Instructions allows the user to select on a per-pin basis + * - 15 + - 14 + - 13 + - 12 + - 11 + - 10 + - 9 + - 8 + - 7 + - 6 + - 5 + - 4 + - 3 + - 2 + - 1 + - 0 + * - rv + - 1 + - 0 + - 0 + - rv + - rv + - rv + - rv + - m + - m + - m + - m + - m + - m + - m + - m + +The CS Invert Mask Instruction allows the user to select on a per-pin basis whether the Chip Select will be active-low (default) or active-high (inverted). -Note that the Chip-Select instructions should remain the same because the value -of CS is inverted at the output register, and additional logic (e.g. reset -counters) occurs when the CS active state is asserted. -Since the physical values on the pins are inverted at the output, the current -Invert Mask does not affect the use of the :ref:`spi_engine cs-instruction`. As -an example, a Chip-Select Instruction with the 's' field equal to 0xFE will +.. note:: + Chip-Select instruction must remain the same since the value of CS is inverted at + the output register. So, current Invert Mask does not affect the use of the + :ref:`spi_engine cs-instruction`. Additional logic (e.g. reset counters) + occurs when the CS active state is asserted. + +For example, a Chip-Select Instruction with the 's' field equal to 0xFE will always result in only CS[0] being active. For an Invert Mask of 0xFF, this would result on only CS[0] being high. For an Invert Mask of 0x00, this would result on only CS[0] being low. For an Invert Mask of 0x01, this would result on all CS pins being high, but only CS[0] is active in this case (since it's the only one currently treated as active-high). -This was introduced in -version 1.02.00 of the core. +**This was introduced in version 1.02.00 of the core.** .. list-table:: :widths: 10 15 75 @@ -222,7 +419,7 @@ version 1.02.00 of the core. * - Bits - Name - Description - * - r + * - rv - reserved - Reserved for future use. Must always be set to 0. * - m @@ -235,15 +432,15 @@ version 1.02.00 of the core. Configuration Registers -------------------------------------------------------------------------------- -The SPI Engine execution module has a set of 8-bit configuration registers which -can be used to dynamically modify the behavior of the module at runtime. +The SPI Engine execution module has a set of 8-bit configuration registers +which can be used to dynamically modify the behavior of the module at runtime. .. _spi_engine spi-configuration-register: SPI Configuration Register ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -The SPI configuration register configures various aspects of the low-level SPI +The SPI configuration register configures several aspects of the low-level SPI bus behavior. .. list-table:: @@ -265,29 +462,81 @@ bus behavior. - Configures the output of the three_wire pin. * - [1] - CPOL - - Configures the polarity of the SCLK signal. When 0, the idle state of - the SCLK signal is low. When 1, the idle state of the SCLK signal is - high. + - Configures the polarity of the SCLK signal: + + - When 0, the idle state of the SCLK signal is low. + - When 1, the idle state of the SCLK signal is high. * - [0] - CPHA - - Configures the phase of the SCLK signal. When 0, data is sampled on the - leading edge and updated on the trailing edge. When 1, data is - sampled on the trailing edge and updated on the leading edge. + - Configures the phase of the SCLK signal: + + - When 0, data is sampled on the leading edge and updated on the + trailing edge. + - When 1, data is sampled on the trailing edge and updated on the + leading edge. + +.. _spi_engine sdi-lane-mask-register: + +SDI Lane Mask Register +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +This register configures the SDI mask that defines which lanes are active +(active-high). The user must define a mask that contains up to ``NUM_OF_SDIO`` +lanes (the number of activated lanes cannot be bigger than the number of lanes). +For now, it is possible to have up to 8 lanes due to the instruction size. + +.. list-table:: + :widths: 10 15 50 + :header-rows: 1 + + * - Bits + - Name + - Description + * - [7:0] + - SDI lane mask + - Only bits set to 1 have their respective lane active. + + +.. _spi_engine sdo-lane-mask-register: + +SDO Lane Mask Register +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +This register configures the SDO mask that defines which lanes are active +(active-high). The user must define a mask that contains up to ``NUM_OF_SDIO`` +lanes (the number of activated lanes cannot be bigger than the number of lanes). +For now, it is possible to have up to 8 lanes due to the instruction size. + +.. list-table:: + :widths: 10 15 50 + :header-rows: 1 + + * - Bits + - Name + - Description + * - [7:0] + - SDO lane mask + - Only bits set to 1 have their respective lane active. .. _spi_engine prescaler-configuration-register: Prescaler Configuration Register ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -The prescaler configuration register configures the divider that is applied to +The prescaler configuration register defines the divider that is applied to the module clock when generating the SCLK signal and other internal control -signals used by the sleep and chip-select commands. +signals used by the sleep and chip-select instructions. -===== ==== ======================= -Bits Name Description -===== ==== ======================= -[7:0] div Prescaler clock divider -===== ==== ======================= +.. list-table:: + :widths: 10 15 30 + :header-rows: 1 + + * - Bits + - Name + - Description + * - [7:0] + - Div + - Prescaler clock divider. The default value of div is 0. The frequency of the SCLK signal is derived from the module clock frequency using the following formula: @@ -296,9 +545,6 @@ using the following formula: f\_{sclk} = \frac{f_{clk}}{((div + 1) * 2)} - -If no prescaler block is present div is 0. - .. _spi_engine dynamic-transfer-length-register: Dynamic Transfer Length Register @@ -306,12 +552,17 @@ Dynamic Transfer Length Register The dynamic transfer length register sets the length (in bits) of a transfer. By default, the transfer length is equal to the DATA_WIDTH of the execution module. -If required the user can reduce this length by setting this register. A general -rule of thumb is to set the DATA_WIDTH parameter to the largest transfer length -supported by the target device. - -===== ==== ======================= -Bits Name Description -===== ==== ======================= -[7:0] div Dynamic transfer length -===== ==== ======================= +If required, the user can reduce this length by setting this register. A +general rule of thumb is to set the DATA_WIDTH parameter to be the largest +transfer length supported by the target device. + +.. list-table:: + :widths: 10 15 30 + :header-rows: 1 + + * - Bits + - Name + - Description + * - [7:0] + - Div + - Dynamic transfer length. diff --git a/docs/library/spi_engine/spi_engine.svg b/docs/library/spi_engine/spi_engine.svg index 0dc20a28b8e..31ee134b6a1 100644 --- a/docs/library/spi_engine/spi_engine.svg +++ b/docs/library/spi_engine/spi_engine.svg @@ -1,125 +1,894 @@ - + - - - - - - - - - - - - - image/svg+xml - - - - - - - - sdi - sdo - - - Data Shift Register - - - SDI - - - - - - - - SDO - - - - - + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + sdi + sdo + + + Data Shift Register - - - - - MultifunctionCounter and CompareUnit - - - - Prescaler - - - - clk - - trigger - - sclk - - Instruction Decoder - - - - - - - CMD - - - - chip-select - - - cs - - CE - - D - Q - - - SYNC - - - - - - - - - - - - - - - Clock Gen - - - - CE - three_wire - - Config - - - - - - - - - - - + + SDI + + + + + + + + SDO + + + + + + + + + + offload active + + + + + + + + + + + MultifunctionCounter and CompareUnit + + + + Prescaler + + + + clk + + trigger + + sclk + + Instruction Decoder + + + + + + + CMD + + + + chip-select + + + cs + + CE + + D + Q + + + SYNC + + + + + + + + + + + + + + + Clock Gen + + + + CE + three_wire + + Config + + + + + + + + + + + + + cphacpol + sleep_compare + + active - cphacpol - sleep_compare - - active - diff --git a/docs/library/spi_engine/spi_engine_execution.rst b/docs/library/spi_engine/spi_engine_execution.rst index b8dcc524bf9..6b4e4e2192a 100644 --- a/docs/library/spi_engine/spi_engine_execution.rst +++ b/docs/library/spi_engine/spi_engine_execution.rst @@ -40,8 +40,8 @@ Configuration Parameters * - DATA_WIDTH - Data width of the parallel data stream. Will define the transaction's granularity. Supported values: 8/16/24/32 - * - NUM_OF_SDI - - Number of multiple SDI lines, (min: 1, max: 8) + * - NUM_OF_SDIO + - Number of multiple SDI/SDO lines, (min: 1, max: 8) Signal and Interface Pins -------------------------------------------------------------------------------- @@ -59,6 +59,8 @@ Signal and Interface Pins - :ref:`spi_engine control-interface` subordinate. SPI Engine Control stream that contains commands and data for the execution module. + * - s_offload_active_ctrl + - | Defines whether offload mode is active or not (active high). * - spi - :ref:`spi_engine spi-bus-interface` controller. Low-level SPI bus interface that is controlled by peripheral. @@ -80,6 +82,11 @@ that translates the incoming commands into an internal control signal, a multi-function counter and compares unit that is responsible for handling the timing and a shift register which holds the received and transmitted SPI data. +The shift register has a different behavior for offload and FIFO mode. Offload +mode needs to have all of its lanes active for allowing prefetch of data, +otherwise it is going to wait for the write instruction. That is controlled +through the ``s_offload_active_ctrl`` interface. + The module has an optional programmable pre-scaler register that can be used to divide the external clock to the counter and compare unit. diff --git a/docs/library/spi_engine/spi_engine_interconnect.rst b/docs/library/spi_engine/spi_engine_interconnect.rst index e9e1e14a87c..8d3861e1079 100644 --- a/docs/library/spi_engine/spi_engine_interconnect.rst +++ b/docs/library/spi_engine/spi_engine_interconnect.rst @@ -8,14 +8,14 @@ SPI Engine Interconnect Module The :git-hdl:`SPI Engine Interconnect ` allows connecting multiple :ref:`spi_engine control-interface` managers to a single :ref:`spi_engine control-interface` subordinate. -This enables multiple command stream generators to connect to a single -:ref:`spi_engine execution` and consequential give them access to the same SPI bus. -The interconnect modules take care of properly arbitrating between the different -command streams. +This enables two command stream generators to connect to a single +:ref:`spi_engine execution` and consequentially give them access to the same SPI bus. +The interconnect module is responsible for proper arbitration between the command +streams. -Combining multiple command stream generators in a design and connecting them to -a single execution module allows for the creation of flexible and efficient -designs using standard components. +Combining two command stream generators in a design and connecting them to a single +execution module allows the creation of an efficient and flexible design by using +standard components. Files -------------------------------------------------------------------------------- @@ -40,8 +40,8 @@ Configuration Parameters * - DATA_WIDTH - Data width of the parallel SDI/SDO data interfaces. - * - NUM_OF_SDI - - Number of SDI lines on the physical SPI interface. + * - NUM_OF_SDIO + - Number of SDI/SDO lines on the physical SPI interface. Signal and Interface Pins @@ -50,33 +50,33 @@ Signal and Interface Pins .. hdl-interfaces:: * - clk - - A signals of the module are synchronous to this clock. + - | * - resetn - - Synchronous active-low reset. - Resets the internal state of the module. + - | Synchronous active-low reset. + | Resets the internal state of the module. * - s0_ctrl - | :ref:`spi_engine control-interface` subordinate. - | Connects to the first control interface manager. + | Connects to the offload control interface manager. * - s1_ctrl - | :ref:`spi_engine control-interface` subordinate. - | Connects to the second control interface manager. + | Connects to the fifo control interface manager. * - m_ctrl - | :ref:`spi_engine control-interface` manager. | Connects to the control interface subordinate. + * - s_interconnect_ctrl + - | m_interconnect_ctrl (:ref:`spi_engine offload`) subordinate. + | Defines whether offload mode is active or not (active high). + * - m_offload_active_ctrl + - | Forwards the signals of the s_interconnect_ctrl interface. + | Defines whether offload mode is active or not (active high). Theory of Operation -------------------------------------------------------------------------------- -The SPI Engine Interconnect module has multiple -:ref:`spi_engine control-interface` subordinate ports and a single -:ref:`spi_engine control-interface` manager port. -It can be used to connect multiple command stream generators to a single command -execution engine. Arbitration between the streams is done on a priority -basis, streams with a lower index have higher priority. This means if commands -are present on two streams arbitration will be granted to the one with the lower -index. Once arbitration has been granted the port it was granted to stays in -control until it sends a SYNC command. When the interconnect module sees a SYNC -command arbitration will be re-evaluated after the SYNC command has been -completed. This makes sure that once a SPI transaction consisting of multiple -commands has been started it is able to complete without being interrupted by a -higher priority stream. +The SPI Engine Interconnect module has two :ref:`spi_engine control-interface` +subordinate ports and a single :ref:`spi_engine control-interface` manager +port. It can be used to connect two command stream generators to a single +command execution engine. Arbitration between streams is done based on the +``s_interconnect_ctrl`` interface, there is a copy of this interface to +``m_offload_active_ctrl`` to indicate whether the stream belongs to offload (s0) or +fifo mode (s1). \ No newline at end of file diff --git a/docs/library/spi_engine/spi_engine_offload.rst b/docs/library/spi_engine/spi_engine_offload.rst index 37b1058a909..8aa19794409 100644 --- a/docs/library/spi_engine/spi_engine_offload.rst +++ b/docs/library/spi_engine/spi_engine_offload.rst @@ -45,8 +45,8 @@ Configuration Parameters * - DATA_WIDTH - Data width of the parallel data stream. Will define the transaction's granularity. Supported values: 8/16/24/32 - * - NUM_OF_SDI - - Number of multiple SDI lines, (min: 1, max: 8) + * - NUM_OF_SDIO + - Number of multiple SDI/SDO lines, (min: 1, max: 8) * - SDO_STREAMING - Enables the s_axis_sdo interface. This allows for sourcing the SDO data stream from a DMA or other similar sources, useful for DACs. @@ -80,3 +80,5 @@ Signal and Interface Pins * - s_axis_sdo - Streaming AXI peripheral Input stream for SPI data to be sent. Only present when ``SDO_STREAMING`` parameter is set to 1. + * - m_interconnect_ctrl + - | Defines whether offload mode is active or not (active high). diff --git a/docs/projects/ad4630_fmc/index.rst b/docs/projects/ad4630_fmc/index.rst index a4ccc1ac443..4960c714200 100644 --- a/docs/projects/ad4630_fmc/index.rst +++ b/docs/projects/ad4630_fmc/index.rst @@ -183,7 +183,7 @@ digital interface: - 0 - SPI mode - 1 - Echo-clock or Master clock mode -The NUM_OF_SDI configuration parameter defines the number of MOSI lines of the +The NUM_OF_SDIO configuration parameter defines the number of MOSI lines of the SPI interface: - 1 - Interleaved mode @@ -351,14 +351,14 @@ the HDL repository, and then build the project as follows:. .. shell:: $cd hdl/projects/ad4630_fmc/zed - $make NUM_OF_SDI=4 CAPTURE_ZONE=2 + $make NUM_OF_SDIO=4 CAPTURE_ZONE=2 The result of the build, if parameters were used, will be in a folder named by the configuration used: if the following command was run -``make NUM_OF_SDI=4 CAPTURE_ZONE=2`` +``make NUM_OF_SDIO=4 CAPTURE_ZONE=2`` then the folder name will be: diff --git a/docs/projects/ad738x_fmc/index.rst b/docs/projects/ad738x_fmc/index.rst index 514ed7b5470..30d633afcc1 100644 --- a/docs/projects/ad738x_fmc/index.rst +++ b/docs/projects/ad738x_fmc/index.rst @@ -112,14 +112,14 @@ In case of the **Alert Indication Output Pin** functionality: $make ALERT_SPI_N=1 -The **NUM_OF_SDI** configuration parameter defines the number of SDI lines used: +The **NUM_OF_SDIO** configuration parameter defines the number of SDI lines used: **{1, 2, 4}**. By default is set to 1. For the **ALERT** functionality, the following parameters will be used in make command: ALERT_SPI_N. For the **serial data output** functionality, the following parameters will be -used in make command: ALERT_SPI_N, NUM_OF_SDI. +used in make command: ALERT_SPI_N, NUM_OF_SDIO. Jumper setup ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -264,14 +264,14 @@ the HDL repository, and then build the project as follows: .. shell:: $cd hdl/projects/ad738x_fmc/zed - $make ALERT_SPI_N=0 NUM_OF_SDI=4 + $make ALERT_SPI_N=0 NUM_OF_SDIO=4 The result of the build, if parameters were used, will be in a folder named by the configuration used: if the following command was run -``make ALERT_SPI_N=0 NUM_OF_SDI=4`` +``make ALERT_SPI_N=0 NUM_OF_SDIO=4`` then the folder name will be: diff --git a/docs/projects/ad7606x_fmc/index.rst b/docs/projects/ad7606x_fmc/index.rst index 08e0f7ffcaf..142eff9eb78 100644 --- a/docs/projects/ad7606x_fmc/index.rst +++ b/docs/projects/ad7606x_fmc/index.rst @@ -125,7 +125,7 @@ In case of the **SERIAL** interface: - JP5 - Position A - Serial interface - JP5 - Position B - Parallel interface -The NUM_OF_SDI configuration parameter defines the number of SDI lines used: +The NUM_OF_SDIO configuration parameter defines the number of SDI lines used: **{1, 2, 4, 8}**. By default is set to 8. The ADC_N_BITS configuration parameter specifies the ADC resolution: diff --git a/docs/projects/ad7616_sdz/index.rst b/docs/projects/ad7616_sdz/index.rst index 232eaad81d4..8aec64c1293 100644 --- a/docs/projects/ad7616_sdz/index.rst +++ b/docs/projects/ad7616_sdz/index.rst @@ -85,7 +85,7 @@ The following are the parameters of this project that can be configured: - 0 - parallel (default) - 1 - serial -- NUM_OF_SDI: number of SDI lines used, **only in serial interface mode**; +- NUM_OF_SDIO: number of SDI lines used, **only in serial interface mode**; - 1 - one SDI line - 2 - two SDI lines (default) @@ -264,14 +264,14 @@ the HDL repository, and then build the project as follows:. .. shell:: $cd hdl/projects/ad7616_sdz/zed - $make INTF=1 NUM_OF_SDI=2 + $make INTF=1 NUM_OF_SDIO=2 The result of the build, if parameters were used, will be in a folder named by the configuration used: if the following command was run -``make INTF=1 NUM_OF_SDI=2`` +``make INTF=1 NUM_OF_SDIO=2`` then the folder name will be: diff --git a/docs/regmap/adi_regmap_spi_engine.txt b/docs/regmap/adi_regmap_spi_engine.txt index 5cd86d6f9ef..caf25574823 100644 --- a/docs/regmap/adi_regmap_spi_engine.txt +++ b/docs/regmap/adi_regmap_spi_engine.txt @@ -9,7 +9,7 @@ ENDTITLE REG 0x00 VERSION -Version of the peripheral. Follows semantic versioning. Current version 1.04.02. +Version of the peripheral. Follows semantic versioning. Current version 1.06.00. ENDREG FIELD @@ -19,13 +19,13 @@ RO ENDFIELD FIELD -[15:8] 0x00000005 +[15:8] 0x00000006 VERSION_MINOR RO ENDFIELD FIELD -[7:0] 0x00000001 +[7:0] 0x00000000 VERSION_PATCH RO ENDFIELD @@ -70,7 +70,7 @@ DATA_WIDTH ENDREG FIELD -[7:4] NUM_OF_SDI +[23:16] NUM_OF_SDI NUM_OF_SDI RO Number of SDI. @@ -78,7 +78,7 @@ It is equal with the maximum supported SDI lines in bits. ENDFIELD FIELD -[3:0] DATA_WIDTH +[15:0] DATA_WIDTH DATA_WIDTH RO Data width of the SDI/SDO parallel interface. @@ -369,21 +369,6 @@ ENDFIELD ############################################################################################ ############################################################################################ -REG -0x3b -SDI_FIFO_MSB -ENDREG - -FIELD -[31:0] -SDI_FIFO_MSB -RO -Store SDI's 32 bits MSB, if exists. -ENDFIELD - -############################################################################################ -############################################################################################ - REG 0x3c SDI_FIFO_PEEK diff --git a/docs/user_guide/ip_cores/use_adi_ips.rst b/docs/user_guide/ip_cores/use_adi_ips.rst index a8865fe4858..992543d00c2 100644 --- a/docs/user_guide/ip_cores/use_adi_ips.rst +++ b/docs/user_guide/ip_cores/use_adi_ips.rst @@ -179,10 +179,10 @@ An example of instantiation, using the default values for ``cmd_mem_addr_width`` .. code:: tcl # name data_width async_spi_clk num_csn num_sdi sdi_delay echo_sclk - spi_engine_create "spi_ad463x" 32 1 1 $NUM_OF_SDI 0 1 + spi_engine_create "spi_ad463x" 32 1 1 $NUM_OF_SDIO 0 1 ad_ip_parameter spi_ad463x/execution CONFIG.DEFAULT_SPI_CFG 1 ; - ad_ip_parameter spi_ad463x/axi_regmap CONFIG.CFG_INFO_0 $NUM_OF_SDI + ad_ip_parameter spi_ad463x/axi_regmap CONFIG.CFG_INFO_0 $NUM_OF_SDIO ad_ip_parameter spi_ad463x/axi_regmap CONFIG.CFG_INFO_1 $CAPTURE_ZONE ad_ip_parameter spi_ad463x/axi_regmap CONFIG.CFG_INFO_2 $CLK_MODE ad_ip_parameter spi_ad463x/axi_regmap CONFIG.CFG_INFO_3 $DDR_EN diff --git a/library/spi_engine/axi_spi_engine/Makefile b/library/spi_engine/axi_spi_engine/Makefile index 19d442d8ab7..9067ac74b04 100644 --- a/library/spi_engine/axi_spi_engine/Makefile +++ b/library/spi_engine/axi_spi_engine/Makefile @@ -20,6 +20,7 @@ XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_offload_ctrl.xml XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_offload_ctrl_rtl.xml XILINX_LIB_DEPS += util_axis_fifo +XILINX_LIB_DEPS += util_axis_fifo_asym XILINX_LIB_DEPS += util_cdc XILINX_INTERFACE_DEPS += spi_engine/interfaces diff --git a/library/spi_engine/axi_spi_engine/axi_spi_engine.v b/library/spi_engine/axi_spi_engine/axi_spi_engine.v index 378b982007a..6a3a78c9571 100644 --- a/library/spi_engine/axi_spi_engine/axi_spi_engine.v +++ b/library/spi_engine/axi_spi_engine/axi_spi_engine.v @@ -48,7 +48,7 @@ module axi_spi_engine #( parameter OFFLOAD0_SDO_MEM_ADDRESS_WIDTH = 4, parameter ID = 0, parameter [15:0] DATA_WIDTH = 8, - parameter [ 7:0] NUM_OF_SDI = 1, + parameter [ 7:0] NUM_OF_SDIO = 1, parameter CFG_INFO_0 = 0, parameter CFG_INFO_1 = 0, parameter CFG_INFO_2 = 0, @@ -106,11 +106,11 @@ module axi_spi_engine #( input sdo_data_ready, output sdo_data_valid, - output [(DATA_WIDTH-1):0] sdo_data, + output [(DATA_WIDTH)-1:0] sdo_data, output sdi_data_ready, input sdi_data_valid, - input [(NUM_OF_SDI * DATA_WIDTH-1):0] sdi_data, + input [(NUM_OF_SDIO * DATA_WIDTH)-1:0] sdi_data, output sync_ready, input sync_valid, @@ -122,7 +122,7 @@ module axi_spi_engine #( output [15:0] offload0_cmd_wr_data, output offload0_sdo_wr_en, - output [(DATA_WIDTH-1):0] offload0_sdo_wr_data, + output [(DATA_WIDTH)-1:0] offload0_sdo_wr_data, output offload0_mem_reset, output offload0_enable, @@ -133,9 +133,10 @@ module axi_spi_engine #( input [7:0] offload_sync_data ); - localparam PCORE_VERSION = 'h010501; + localparam PCORE_VERSION = 'h010600; localparam S_AXI = 0; localparam UP_FIFO = 1; + localparam max_num_of_reads = NUM_OF_SDIO-1; wire clk; wire rstn; @@ -152,18 +153,21 @@ module axi_spi_engine #( wire sdo_fifo_almost_empty; wire up_sdo_fifo_almost_empty; - wire [(DATA_WIDTH-1):0] sdo_fifo_in_data; + wire [DATA_WIDTH-1:0] sdo_fifo_in_data; wire sdo_fifo_in_ready; wire sdo_fifo_in_valid; - wire sdi_fifo_out_data_msb_s; - wire [SDI_FIFO_ADDRESS_WIDTH-1:0] sdi_fifo_level; + wire [31:0] sdi_fifo_level; + reg [NUM_OF_SDIO*DATA_WIDTH/8-1:0] sdi_fifo_tkeep_int; + wire [NUM_OF_SDIO*DATA_WIDTH/8-1:0] sdi_fifo_tkeep; wire sdi_fifo_almost_full; wire up_sdi_fifo_almost_full; - wire [(NUM_OF_SDI * DATA_WIDTH-1):0] sdi_fifo_out_data; + wire [DATA_WIDTH-1:0] sdi_fifo_out_data; wire sdi_fifo_out_ready; + reg find_next_valid_fifo_value; wire sdi_fifo_out_valid; + reg [3:0] sdi_out_counter; wire [7:0] sync_fifo_data; wire sync_fifo_valid; @@ -317,23 +321,6 @@ module axi_spi_engine #( end end - always @(posedge clk) begin - if (rstn == 1'b0) begin - up_rack_ff <= 'd0; - end else begin - up_rack_ff <= up_rreq_s; - end - end - - generate - if (NUM_OF_SDI > 1) begin - // Only the first two SDI data can be recovered through AXI regmap - assign sdi_fifo_out_data_msb_s = sdi_fifo_out_data[DATA_WIDTH+:DATA_WIDTH]; - end else begin - assign sdi_fifo_out_data_msb_s = sdi_fifo_out_data; - end - endgenerate - reg [7:0] offload_sdo_mem_address_width = OFFLOAD0_SDO_MEM_ADDRESS_WIDTH; reg [7:0] offload_cmd_mem_address_width = OFFLOAD0_CMD_MEM_ADDRESS_WIDTH; reg [7:0] sdi_fifo_address_width = SDI_FIFO_ADDRESS_WIDTH; @@ -345,7 +332,7 @@ module axi_spi_engine #( 8'h00: up_rdata_ff <= PCORE_VERSION; 8'h01: up_rdata_ff <= ID; 8'h02: up_rdata_ff <= up_scratch; - 8'h03: up_rdata_ff <= {8'b0, NUM_OF_SDI, DATA_WIDTH}; + 8'h03: up_rdata_ff <= {8'b0, NUM_OF_SDIO, DATA_WIDTH}; 8'h04: up_rdata_ff <= {16'b0, offload_sdo_mem_address_width, offload_cmd_mem_address_width}; 8'h05: up_rdata_ff <= {sdi_fifo_address_width, sdo_fifo_address_width, sync_fifo_address_width, cmd_fifo_address_width}; 8'h10: up_rdata_ff <= up_sw_reset; @@ -356,10 +343,9 @@ module axi_spi_engine #( 8'h31: up_rdata_ff <= offload_sync_id; 8'h34: up_rdata_ff <= cmd_fifo_room; 8'h35: up_rdata_ff <= sdo_fifo_room; - 8'h36: up_rdata_ff <= (sdi_fifo_out_valid == 1) ? sdi_fifo_level + 1 : sdi_fifo_level; /* beacuse of first-word-fall-through */ + 8'h36: up_rdata_ff <= (sdi_fifo_out_valid == 1) ? sdi_fifo_level + 1 : sdi_fifo_level; /* because of first-word-fall-through */ 8'h3a: up_rdata_ff <= sdi_fifo_out_data[DATA_WIDTH-1:0]; - 8'h3b: up_rdata_ff <= sdi_fifo_out_data_msb_s; /* store SDI's 32 bits MSB, if exists */ - 8'h3c: up_rdata_ff <= sdi_fifo_out_data; /* PEEK register */ + 8'h3c: up_rdata_ff <= sdi_fifo_out_data[DATA_WIDTH-1:0]; /* PEEK register */ 8'h40: up_rdata_ff <= {offload0_enable_reg}; 8'h41: up_rdata_ff <= {offload0_enabled_s}; 8'h80: up_rdata_ff <= CFG_INFO_0; @@ -421,7 +407,9 @@ module axi_spi_engine #( .ASYNC_CLK(ASYNC_SPI_CLK), .M_AXIS_REGISTERED(0), .ALMOST_EMPTY_THRESHOLD(1), - .ALMOST_FULL_THRESHOLD(1) + .ALMOST_FULL_THRESHOLD(1), + .TLAST_EN(0), + .TKEEP_EN(0) ) i_cmd_fifo ( .s_axis_aclk(clk), .s_axis_aresetn(up_sw_resetn), @@ -430,20 +418,23 @@ module axi_spi_engine #( .s_axis_data(cmd_fifo_in_data), .s_axis_room(cmd_fifo_room), .s_axis_tlast(1'b0), + .s_axis_tkeep(), .s_axis_full(), .s_axis_almost_full(), + .m_axis_aclk(spi_clk), .m_axis_aresetn(spi_resetn), .m_axis_ready(cmd_ready), .m_axis_valid(cmd_valid), .m_axis_data(cmd_data), .m_axis_tlast(), + .m_axis_tkeep(), + .m_axis_level(), .m_axis_empty(), - .m_axis_almost_empty(cmd_fifo_almost_empty), - .m_axis_level()); + .m_axis_almost_empty(cmd_fifo_almost_empty)); assign sdo_fifo_in_valid = up_wreq_s == 1'b1 && up_waddr_s == 8'h39; - assign sdo_fifo_in_data = up_wdata_s[(DATA_WIDTH-1):0]; + assign sdo_fifo_in_data = up_wdata_s[DATA_WIDTH-1:0]; util_axis_fifo #( .DATA_WIDTH(DATA_WIDTH), @@ -460,6 +451,7 @@ module axi_spi_engine #( .s_axis_data(sdo_fifo_in_data), .s_axis_room(sdo_fifo_room), .s_axis_tlast(1'b0), + .s_axis_tkeep(), .s_axis_full(), .s_axis_almost_full(), .m_axis_aclk(spi_clk), @@ -468,20 +460,39 @@ module axi_spi_engine #( .m_axis_valid(sdo_data_valid), .m_axis_data(sdo_data), .m_axis_tlast(), + .m_axis_tkeep(), .m_axis_level(), .m_axis_empty(), .m_axis_almost_empty(sdo_fifo_almost_empty)); assign sdi_fifo_out_ready = up_rreq_s == 1'b1 && up_raddr_s == 8'h3a; - util_axis_fifo #( - .DATA_WIDTH(NUM_OF_SDI * DATA_WIDTH), + integer i; + always @(posedge spi_clk) begin + if (!spi_resetn) begin + sdi_fifo_tkeep_int <= {(NUM_OF_SDIO*DATA_WIDTH/8){1'b1}}; + end else begin + if (cmd_valid && cmd_data[15:8] == 8'h23) begin + for (i = 0; i < NUM_OF_SDIO; i = i + 1) begin + sdi_fifo_tkeep_int[i*DATA_WIDTH/8+:DATA_WIDTH/8] <= {DATA_WIDTH/8{cmd_data[i]}}; + end + end + end + end + assign sdi_fifo_tkeep = sdi_fifo_tkeep_int; + + util_axis_fifo_asym #( .ASYNC_CLK(ASYNC_SPI_CLK), - .ADDRESS_WIDTH(SDI_FIFO_ADDRESS_WIDTH), + .S_DATA_WIDTH(NUM_OF_SDIO * DATA_WIDTH), + .M_DATA_WIDTH(DATA_WIDTH), + .ADDRESS_WIDTH(SDO_FIFO_ADDRESS_WIDTH), .M_AXIS_REGISTERED(0), .ALMOST_EMPTY_THRESHOLD(1), - .ALMOST_FULL_THRESHOLD(31) - ) i_sdi_fifo ( + .ALMOST_FULL_THRESHOLD(1), + .TLAST_EN(0), + .TKEEP_EN(1), + .REDUCED_FIFO(0) + ) i_sdi_fifo( .s_axis_aclk(spi_clk), .s_axis_aresetn(spi_resetn), .s_axis_ready(sdi_data_ready), @@ -489,18 +500,53 @@ module axi_spi_engine #( .s_axis_data(sdi_data), .s_axis_room(), .s_axis_tlast(), + .s_axis_tkeep(sdi_fifo_tkeep), .s_axis_full(), .s_axis_almost_full(sdi_fifo_almost_full), .m_axis_aclk(clk), .m_axis_aresetn(up_sw_resetn), - .m_axis_ready(sdi_fifo_out_ready), + .m_axis_ready(sdi_fifo_out_ready || find_next_valid_fifo_value), .m_axis_valid(sdi_fifo_out_valid), .m_axis_data(sdi_fifo_out_data), .m_axis_tlast(), + .m_axis_tkeep(), .m_axis_level(sdi_fifo_level), .m_axis_empty(), .m_axis_almost_empty()); + assign sdi_fifo_out_ready = up_rreq_s == 1'b1 && up_raddr_s == 8'h3a; + + always @(posedge clk) begin + if (rstn == 1'b0) begin + up_rack_ff <= 'd0; + end else begin + if (sdi_fifo_out_ready || find_next_valid_fifo_value) begin + up_rack_ff <= sdi_fifo_out_valid; + end else begin + up_rack_ff <= up_rreq_s; + end + end + end + + //the current logic is considering that there is only one active lane in the set of lanes + always @(posedge clk) begin + if (!up_sw_resetn) begin + find_next_valid_fifo_value <= 1'b0; + sdi_out_counter <= 4'hf; + end else if (sdi_fifo_out_ready) begin + find_next_valid_fifo_value <= ~sdi_fifo_out_valid; //only in the next cycle it is possible to check if it is necessary a new read + sdi_out_counter <= sdi_fifo_out_valid ? 4'hf : 0; + end else begin + if (!sdi_fifo_out_valid && sdi_out_counter < max_num_of_reads) begin + find_next_valid_fifo_value <= 1'b1; + sdi_out_counter <= sdi_out_counter + 1'b1; + end else begin + find_next_valid_fifo_value <= 1'b0; + sdi_out_counter <= 4'hf; + end + end + end + generate if (ASYNC_SPI_CLK) begin // synchronization FIFO for the SYNC interface @@ -508,7 +554,9 @@ module axi_spi_engine #( .DATA_WIDTH(8), .ASYNC_CLK(ASYNC_SPI_CLK), .ADDRESS_WIDTH(SYNC_FIFO_ADDRESS_WIDTH), - .M_AXIS_REGISTERED(0) + .M_AXIS_REGISTERED(0), + .TLAST_EN(0), + .TKEEP_EN(0) ) i_sync_fifo ( .s_axis_aclk(spi_clk), .s_axis_aresetn(spi_resetn), @@ -516,14 +564,21 @@ module axi_spi_engine #( .s_axis_valid(sync_valid), .s_axis_data(sync_data), .s_axis_room(), + .s_axis_tlast(), + .s_axis_tkeep(), .s_axis_full(), + .s_axis_almost_full(), + .m_axis_aclk(clk), .m_axis_aresetn(up_sw_resetn), .m_axis_ready(1'b1), .m_axis_valid(sync_fifo_valid), .m_axis_data(sync_fifo_data), + .m_axis_tlast(), + .m_axis_tkeep(), .m_axis_level(), - .m_axis_empty()); + .m_axis_empty(), + .m_axis_almost_empty()); // synchronization FIFO for the offload command interface wire up_offload0_cmd_wr_en_s; @@ -533,7 +588,9 @@ module axi_spi_engine #( .DATA_WIDTH(16), .ASYNC_CLK(ASYNC_SPI_CLK), .ADDRESS_WIDTH(SYNC_FIFO_ADDRESS_WIDTH), - .M_AXIS_REGISTERED(0) + .M_AXIS_REGISTERED(0), + .TLAST_EN(0), + .TKEEP_EN(0) ) i_offload_cmd_fifo ( .s_axis_aclk(clk), .s_axis_aresetn(up_sw_resetn), @@ -541,27 +598,36 @@ module axi_spi_engine #( .s_axis_valid(up_offload0_cmd_wr_en_s), .s_axis_data(up_offload0_cmd_wr_data_s), .s_axis_room(), + .s_axis_tlast(), + .s_axis_tkeep(), .s_axis_full(), + .s_axis_almost_full(), + .m_axis_aclk(spi_clk), .m_axis_aresetn(spi_resetn), .m_axis_ready(1'b1), .m_axis_valid(offload0_cmd_wr_en), .m_axis_data(offload0_cmd_wr_data), + .m_axis_tlast(), + .m_axis_tkeep(), .m_axis_level(), - .m_axis_empty()); + .m_axis_empty(), + .m_axis_almost_empty()); assign up_offload0_cmd_wr_en_s = up_wreq_s == 1'b1 && up_waddr_s == 8'h44; assign up_offload0_cmd_wr_data_s = up_wdata_s[15:0]; // synchronization FIFO for the offload SDO interface wire up_offload0_sdo_wr_en_s; - wire [DATA_WIDTH-1:0] up_offload0_sdo_wr_data_s; + wire [(DATA_WIDTH-1):0] up_offload0_sdo_wr_data_s; util_axis_fifo #( .DATA_WIDTH(DATA_WIDTH), .ASYNC_CLK(ASYNC_SPI_CLK), .ADDRESS_WIDTH(SYNC_FIFO_ADDRESS_WIDTH), - .M_AXIS_REGISTERED(0) + .M_AXIS_REGISTERED(0), + .TLAST_EN(0), + .TKEEP_EN(0) ) i_offload_sdo_fifo ( .s_axis_aclk(clk), .s_axis_aresetn(up_sw_resetn), @@ -569,14 +635,21 @@ module axi_spi_engine #( .s_axis_valid(up_offload0_sdo_wr_en_s), .s_axis_data(up_offload0_sdo_wr_data_s), .s_axis_room(), + .s_axis_tlast(), + .s_axis_tkeep(), .s_axis_full(), + .s_axis_almost_full(), + .m_axis_aclk(spi_clk), .m_axis_aresetn(spi_resetn), .m_axis_ready(1'b1), .m_axis_valid(offload0_sdo_wr_en), .m_axis_data(offload0_sdo_wr_data), + .m_axis_tlast(), + .m_axis_tkeep(), .m_axis_level(), - .m_axis_empty()); + .m_axis_empty(), + .m_axis_almost_empty()); assign up_offload0_sdo_wr_en_s = up_wreq_s == 1'b1 && up_waddr_s == 8'h45; assign up_offload0_sdo_wr_data_s = up_wdata_s[DATA_WIDTH-1:0]; @@ -586,7 +659,9 @@ module axi_spi_engine #( .DATA_WIDTH(8), .ASYNC_CLK(ASYNC_SPI_CLK), .ADDRESS_WIDTH(SYNC_FIFO_ADDRESS_WIDTH), - .M_AXIS_REGISTERED(0) + .M_AXIS_REGISTERED(0), + .TLAST_EN(0), + .TKEEP_EN(0) ) i_offload_sync_fifo ( .s_axis_aclk(spi_clk), .s_axis_aresetn(spi_resetn), @@ -594,14 +669,21 @@ module axi_spi_engine #( .s_axis_valid(offload_sync_valid), .s_axis_data(offload_sync_data), .s_axis_room(), + .s_axis_tlast(), + .s_axis_tkeep(), .s_axis_full(), + .s_axis_almost_full(), + .m_axis_aclk(clk), .m_axis_aresetn(up_sw_resetn), .m_axis_ready(1'b1), .m_axis_valid(offload_sync_fifo_valid), .m_axis_data(offload_sync_fifo_data), + .m_axis_tlast(), + .m_axis_tkeep(), .m_axis_level(), - .m_axis_empty()); + .m_axis_empty(), + .m_axis_almost_empty()); end else begin /* ASYNC_SPI_CLK == 0 */ diff --git a/library/spi_engine/axi_spi_engine/axi_spi_engine_hw.tcl b/library/spi_engine/axi_spi_engine/axi_spi_engine_hw.tcl index 8f9e2f5d450..be47f18fb2f 100644 --- a/library/spi_engine/axi_spi_engine/axi_spi_engine_hw.tcl +++ b/library/spi_engine/axi_spi_engine/axi_spi_engine_hw.tcl @@ -33,7 +33,7 @@ ad_ip_parameter OFFLOAD0_CMD_MEM_ADDRESS_WIDTH INTEGER 4 ad_ip_parameter OFFLOAD0_SDO_MEM_ADDRESS_WIDTH INTEGER 4 ad_ip_parameter ID INTEGER 0 ad_ip_parameter DATA_WIDTH INTEGER 8 -ad_ip_parameter NUM_OF_SDI INTEGER 1 +ad_ip_parameter NUM_OF_SDIO INTEGER 1 proc p_elaboration {} { @@ -41,7 +41,7 @@ proc p_elaboration {} { set mm_if_type [get_parameter_value "MM_IF_TYPE"] - set num_of_sdi [get_parameter_value NUM_OF_SDI] + set num_of_sdi [get_parameter_value NUM_OF_SDIO] set data_width [get_parameter_value DATA_WIDTH] # interrupt diff --git a/library/spi_engine/axi_spi_engine/axi_spi_engine_ip.tcl b/library/spi_engine/axi_spi_engine/axi_spi_engine_ip.tcl index b775c377c78..44a6d2cc231 100644 --- a/library/spi_engine/axi_spi_engine/axi_spi_engine_ip.tcl +++ b/library/spi_engine/axi_spi_engine/axi_spi_engine_ip.tcl @@ -24,6 +24,7 @@ adi_ip_ttcl axi_spi_engine "axi_spi_engine_constr.ttcl" adi_ip_add_core_dependencies [list \ analog.com:$VIVADO_IP_LIBRARY:util_axis_fifo:1.0 \ analog.com:$VIVADO_IP_LIBRARY:util_cdc:1.0 \ + analog.com:$VIVADO_IP_LIBRARY:util_axis_fifo_asym:1.0 \ ] set_property company_url {https://wiki.analog.com/resources/fpga/peripherals/spi_engine/axi} [ipx::current_core] @@ -194,13 +195,13 @@ set_property -dict [list \ ] \ [ipx::get_user_parameters DATA_WIDTH -of_objects $cc] -## NUM_OF_SDI +## NUM_OF_SDIO set_property -dict [list \ "value_validation_type" "range_long" \ "value_validation_range_minimum" "1" \ "value_validation_range_maximum" "8" \ ] \ - [ipx::get_user_parameters NUM_OF_SDI -of_objects $cc] + [ipx::get_user_parameters NUM_OF_SDIO -of_objects $cc] ## Customize IP Layout @@ -227,11 +228,11 @@ set_property -dict [list \ "tooltip" "\[DATA_WIDTH\] Define the data interface width" ] [ipgui::get_guiparamspec -name "DATA_WIDTH" -component $cc] -ipgui::add_param -name "NUM_OF_SDI" -component $cc -parent $general_group +ipgui::add_param -name "NUM_OF_SDIO" -component $cc -parent $general_group set_property -dict [list \ - "display_name" "Number of MISO lines" \ - "tooltip" "\[NUM_OF_SDI\] Define the number of MISO lines" \ -] [ipgui::get_guiparamspec -name "NUM_OF_SDI" -component $cc] + "display_name" "Number of MISO/MOSI lines" \ + "tooltip" "\[NUM_OF_SDIO\] Define the number of MISO/MOSI lines" \ +] [ipgui::get_guiparamspec -name "NUM_OF_SDIO" -component $cc] ipgui::add_param -name "MM_IF_TYPE" -component $cc -parent $general_group set_property -dict [list \ diff --git a/library/spi_engine/axi_spi_engine/axi_spi_engine_ltt.tcl b/library/spi_engine/axi_spi_engine/axi_spi_engine_ltt.tcl index 1cdcb38f060..2413c4301d1 100755 --- a/library/spi_engine/axi_spi_engine/axi_spi_engine_ltt.tcl +++ b/library/spi_engine/axi_spi_engine/axi_spi_engine_ltt.tcl @@ -115,11 +115,11 @@ set ip [ipl::set_parameter -ip $ip \ -group1 {General Configuration} \ -group2 Config] set ip [ipl::set_parameter -ip $ip \ - -id NUM_OF_SDI \ + -id NUM_OF_SDIO \ -type param \ -value_type int \ -conn_mod axi_spi_engine \ - -title {Number of MISO lines} \ + -title {Number of MISO/MOSI lines} \ -default 1 \ -output_formatter nostr \ -value_range {(1, 8)} \ diff --git a/library/spi_engine/scripts/spi_engine.tcl b/library/spi_engine/scripts/spi_engine.tcl index 0b22305e30a..19b4c982e8d 100644 --- a/library/spi_engine/scripts/spi_engine.tcl +++ b/library/spi_engine/scripts/spi_engine.tcl @@ -33,7 +33,7 @@ proc spi_engine_create {{name "spi_engine"} {data_width 32} {async_spi_clk 1} {n ad_ip_instance spi_engine_execution $execution ad_ip_parameter $execution CONFIG.DATA_WIDTH $data_width ad_ip_parameter $execution CONFIG.NUM_OF_CS $num_cs - ad_ip_parameter $execution CONFIG.NUM_OF_SDI $num_sdi + ad_ip_parameter $execution CONFIG.NUM_OF_SDIO $num_sdi ad_ip_parameter $execution CONFIG.SDO_DEFAULT 1 ad_ip_parameter $execution CONFIG.SDI_DELAY $sdi_delay ad_ip_parameter $execution CONFIG.ECHO_SCLK $echo_sclk @@ -41,7 +41,7 @@ proc spi_engine_create {{name "spi_engine"} {data_width 32} {async_spi_clk 1} {n ad_ip_instance axi_spi_engine $axi_regmap ad_ip_parameter $axi_regmap CONFIG.DATA_WIDTH $data_width ad_ip_parameter $axi_regmap CONFIG.NUM_OFFLOAD 1 - ad_ip_parameter $axi_regmap CONFIG.NUM_OF_SDI $num_sdi + ad_ip_parameter $axi_regmap CONFIG.NUM_OF_SDIO $num_sdi ad_ip_parameter $axi_regmap CONFIG.ASYNC_SPI_CLK $async_spi_clk ad_ip_parameter $axi_regmap CONFIG.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH $cmd_mem_addr_width ad_ip_parameter $axi_regmap CONFIG.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH $data_mem_addr_width @@ -53,14 +53,14 @@ proc spi_engine_create {{name "spi_engine"} {data_width 32} {async_spi_clk 1} {n ad_ip_instance spi_engine_offload $offload ad_ip_parameter $offload CONFIG.DATA_WIDTH $data_width ad_ip_parameter $offload CONFIG.ASYNC_SPI_CLK 0 - ad_ip_parameter $offload CONFIG.NUM_OF_SDI $num_sdi + ad_ip_parameter $offload CONFIG.NUM_OF_SDIO $num_sdi ad_ip_parameter $offload CONFIG.CMD_MEM_ADDRESS_WIDTH $cmd_mem_addr_width ad_ip_parameter $offload CONFIG.SDO_MEM_ADDRESS_WIDTH $data_mem_addr_width ad_ip_parameter $offload CONFIG.SDO_STREAMING $sdo_streaming ad_ip_instance spi_engine_interconnect $interconnect ad_ip_parameter $interconnect CONFIG.DATA_WIDTH $data_width - ad_ip_parameter $interconnect CONFIG.NUM_OF_SDI $num_sdi + ad_ip_parameter $interconnect CONFIG.NUM_OF_SDIO $num_sdi ad_connect $axi_regmap/spi_engine_offload_ctrl0 $offload/spi_engine_offload_ctrl ad_connect $offload/m_interconnect_ctrl $interconnect/s_interconnect_ctrl @@ -71,6 +71,7 @@ proc spi_engine_create {{name "spi_engine"} {data_width 32} {async_spi_clk 1} {n ad_connect $offload/trigger trigger ad_connect $execution/spi m_spi + ad_connect $interconnect/m_offload_active_ctrl $execution/s_offload_active_ctrl if {$sdo_streaming == 1} { ad_connect $offload/s_axis_sdo s_axis_sample diff --git a/library/spi_engine/spi_engine_execution/Makefile b/library/spi_engine/spi_engine_execution/Makefile index 34b7f1e7039..a1239d2354e 100644 --- a/library/spi_engine/spi_engine_execution/Makefile +++ b/library/spi_engine/spi_engine_execution/Makefile @@ -8,6 +8,7 @@ LIBRARY_NAME := spi_engine_execution GENERIC_DEPS += spi_engine_execution.v GENERIC_DEPS += spi_engine_execution_shiftreg.v +GENERIC_DEPS += spi_engine_execution_shiftreg_data_assemble.v XILINX_DEPS += spi_engine_execution_constr.ttcl XILINX_DEPS += spi_engine_execution_ip.tcl @@ -16,6 +17,8 @@ XILINX_DEPS += ../../spi_engine/interfaces/spi_engine.xml XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl.xml XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl_rtl.xml XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_rtl.xml +XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_interconnect_ctrl.xml +XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_interconnect_ctrl_rtl.xml XILINX_INTERFACE_DEPS += spi_engine/interfaces diff --git a/library/spi_engine/spi_engine_execution/spi_engine_execution.v b/library/spi_engine/spi_engine_execution/spi_engine_execution.v index f64c1155f55..d1648a6be04 100644 --- a/library/spi_engine/spi_engine_execution/spi_engine_execution.v +++ b/library/spi_engine/spi_engine_execution/spi_engine_execution.v @@ -41,13 +41,14 @@ module spi_engine_execution #( parameter DEFAULT_SPI_CFG = 0, parameter DEFAULT_CLK_DIV = 0, parameter DATA_WIDTH = 8, // Valid data widths values are 8/16/24/32 - parameter NUM_OF_SDI = 1, + parameter NUM_OF_SDIO = 1, parameter [0:0] SDO_DEFAULT = 1'b0, parameter ECHO_SCLK = 0, parameter [1:0] SDI_DELAY = 2'b00 ) ( input clk, input resetn, + input s_offload_active, output reg active, @@ -57,11 +58,11 @@ module spi_engine_execution #( input sdo_data_valid, output sdo_data_ready, - input [(DATA_WIDTH-1):0] sdo_data, + input [(DATA_WIDTH)-1:0] sdo_data, input sdi_data_ready, output sdi_data_valid, - output [(NUM_OF_SDI * DATA_WIDTH)-1:0] sdi_data, + output [(NUM_OF_SDIO * DATA_WIDTH)-1:0] sdi_data, input sync_ready, output reg sync_valid, @@ -69,9 +70,9 @@ module spi_engine_execution #( input echo_sclk, output reg sclk, - output reg sdo, + output reg [NUM_OF_SDIO-1:0] sdo, output reg sdo_t, - input [NUM_OF_SDI-1:0] sdi, + input [NUM_OF_SDIO-1:0] sdi, output reg [NUM_OF_CS-1:0] cs, output reg three_wire ); @@ -85,9 +86,12 @@ module spi_engine_execution #( localparam MISC_SYNC = 1'b0; localparam MISC_SLEEP = 1'b1; - localparam REG_CLK_DIV = 2'b00; - localparam REG_CONFIG = 2'b01; - localparam REG_WORD_LENGTH = 2'b10; + localparam REG_CLK_DIV = 3'b000; + localparam REG_CONFIG = 3'b001; + localparam REG_WORD_LENGTH = 3'b010; + localparam REG_SDI_LANE_CONFIG = 3'b011; + localparam REG_SDO_LANE_CONFIG = 3'b100; + localparam ALL_ACTIVE_LANE_MASK = (2 ** NUM_OF_SDIO) - 1; //by default all lanes are enabled localparam BIT_COUNTER_WIDTH = DATA_WIDTH > 16 ? 5 : DATA_WIDTH > 8 ? 4 : 3; @@ -122,10 +126,8 @@ module spi_engine_execution #( reg [7:0] word_length = DATA_WIDTH; reg [7:0] last_bit_count = DATA_WIDTH-1; reg [7:0] left_aligned = 8'b0; - - assign first_bit = ((bit_counter == 'h0) || (bit_counter == word_length)); - - reg [15:0] cmd_d1; + reg [7:0] sdi_lane_mask = ALL_ACTIVE_LANE_MASK; + reg [7:0] sdo_lane_mask = ALL_ACTIVE_LANE_MASK; reg cpha = DEFAULT_SPI_CFG[0]; reg cpol = DEFAULT_SPI_CFG[1]; @@ -136,34 +138,44 @@ module spi_engine_execution #( reg sdo_enabled = 1'b0; reg sdi_enabled = 1'b0; + reg [7:0] num_of_transfers = 0; wire sdo_enabled_io; wire sdi_enabled_io; - wire sdo_int_s; + wire [NUM_OF_SDIO-1:0] sdo_int_s; - wire last_bit; + reg last_bit; wire echo_last_bit; - wire first_bit; + reg first_bit; wire end_of_word; - wire [2:0] inst = cmd[14:12]; - wire [2:0] inst_d1 = cmd_d1[14:12]; + //command decoder + wire [2:0] inst = cmd[14:12]; + wire exec_cmd = cmd_ready && cmd_valid; + wire exec_transfer_cmd = exec_cmd && inst == CMD_TRANSFER; + wire exec_chipselect_cmd = exec_cmd && inst == CMD_CHIPSELECT; + wire exec_write_cmd = exec_cmd && inst == CMD_WRITE; + wire exec_misc_cmd = exec_cmd && inst == CMD_MISC; + wire exec_cs_inv_cmd = exec_cmd && inst == CMD_CS_INV; + wire exec_sync_cmd = exec_misc_cmd && cmd[8] == MISC_SYNC; - wire exec_cmd = cmd_ready && cmd_valid; - wire exec_transfer_cmd = exec_cmd && inst == CMD_TRANSFER; - wire exec_cs_inv_cmd = exec_cmd && inst == CMD_CS_INV; - wire exec_write_cmd = exec_cmd && inst == CMD_WRITE; - wire exec_chipselect_cmd = exec_cmd && inst == CMD_CHIPSELECT; - wire exec_misc_cmd = exec_cmd && inst == CMD_MISC; - wire exec_sync_cmd = exec_misc_cmd && cmd[8] == MISC_SYNC; + reg [15:0] cmd_d1; + reg [ 7:0] cmd_d1_time; + reg [ 1:0] cmd_d1_delay; + reg [ 2:0] cmd_d1_instr; + reg cmd_d1_sleep_instr; + reg exec_transfer_cmd_reg = 1'b0; //avoid comparison in the shiftreg + reg exec_write_cmd_reg = 1'b0; //avoid comparison in the shiftreg data assemble + reg exec_sdo_lane_config_reg = 1'b0; //avoid comparison in the shiftreg data assemble + reg exec_chipselect_cmd_reg = 1'b0; //avoid comparison cs_gen + reg cmd_d1_time_is_zero; wire trigger_tx; wire trigger_rx; - wire [1:0] cs_sleep_counter = sleep_counter[1:0]; - wire sleep_counter_compare; - wire cs_sleep_counter_compare; - wire cs_sleep_early_exit; + reg sleep_counter_compare; + reg cs_sleep_counter_compare; + reg cs_sleep_early_exit; reg cs_sleep_repeat; reg cs_activate; @@ -176,14 +188,17 @@ module spi_engine_execution #( spi_engine_execution_shiftreg #( .DEFAULT_SPI_CFG(DEFAULT_SPI_CFG), + .ALL_ACTIVE_LANE_MASK(ALL_ACTIVE_LANE_MASK), .DATA_WIDTH(DATA_WIDTH), - .NUM_OF_SDI(NUM_OF_SDI), + .NUM_OF_SDIO(NUM_OF_SDIO), .SDI_DELAY(SDI_DELAY), .ECHO_SCLK(ECHO_SCLK), - .CMD_TRANSFER(CMD_TRANSFER) + .CMD_TRANSFER(CMD_TRANSFER), + .CMD_WRITE(CMD_WRITE) ) shiftreg ( .clk(clk), .resetn(resetn), + .s_offload_active(s_offload_active), .sdi(sdi), .sdo_int(sdo_int_s), .echo_sclk(echo_sclk), @@ -196,9 +211,12 @@ module spi_engine_execution #( .sdo_enabled(sdo_enabled), .sdi_enabled(sdi_enabled), .current_cmd(cmd_d1), + .exec_cmd(exec_transfer_cmd_reg), + .exec_sdo_lane_cmd(exec_sdo_lane_config_reg), .sdo_idle_state(sdo_idle_state), .left_aligned(left_aligned), .word_length(word_length), + .sdo_lane_mask(sdo_lane_mask), .sdo_io_ready(sdo_io_ready), .echo_last_bit(echo_last_bit), .transfer_active(transfer_active), @@ -207,33 +225,46 @@ module spi_engine_execution #( .first_bit(first_bit), .cs_activate(cs_activate)); - assign cs_gen = inst_d1 == CMD_CHIPSELECT - && ((cs_sleep_counter_compare == 1'b1) || cs_sleep_early_exit) - && (cs_sleep_repeat == 1'b0) - && (idle == 1'b0); + assign cs_gen = exec_chipselect_cmd_reg + && (cs_sleep_counter_compare || cs_sleep_early_exit) + && (~cs_sleep_repeat) && (~idle); assign cmd_ready = idle; always @(posedge clk) begin if (exec_transfer_cmd) begin sdo_enabled <= cmd[8]; sdi_enabled <= cmd[9]; + num_of_transfers <= cmd[7:0]; end end assign sdo_enabled_io = (exec_transfer_cmd) ? cmd[8] : sdo_enabled; assign sdi_enabled_io = (exec_transfer_cmd) ? cmd[9] : sdi_enabled; always @(posedge clk) begin - if (cmd_ready & cmd_valid) - cmd_d1 <= cmd; + if (exec_cmd) begin + cmd_d1 <= cmd; + cmd_d1_instr <= cmd[14:12]; + cmd_d1_delay <= cmd[9:8]; + cmd_d1_sleep_instr <= cmd[8]; + cmd_d1_time <= cmd[7:0]; + cs_sleep_early_exit <= ~|cmd[9:8]; + cmd_d1_time_is_zero <= ~|cmd[7:0]; + exec_transfer_cmd_reg <= (inst == CMD_TRANSFER); + exec_write_cmd_reg <= (inst == CMD_WRITE); + exec_chipselect_cmd_reg <= (inst == CMD_CHIPSELECT); + exec_sdo_lane_config_reg <= (inst == CMD_WRITE) && (cmd[10:8] == REG_SDO_LANE_CONFIG); + end else begin + sleep_counter_compare <= sleep_counter == cmd_d1_time && clk_div_last && sleep_counter_increment; + end end always @(posedge clk) begin - if (resetn == 1'b0) begin + if (!resetn) begin active <= 1'b0; end else begin - if (exec_cmd == 1'b1) + if (exec_cmd) active <= 1'b1; - else if (sync_ready == 1'b1 && sync_valid == 1'b1) + else if (sync_ready && sync_valid) active <= 1'b0; end end @@ -241,26 +272,42 @@ module spi_engine_execution #( // Load the interface configurations from the 'Configuration Write' // instruction always @(posedge clk) begin - if (resetn == 1'b0) begin - cpha <= DEFAULT_SPI_CFG[0]; - cpol <= DEFAULT_SPI_CFG[1]; - three_wire <= DEFAULT_SPI_CFG[2]; + if (!resetn) begin + cpha <= DEFAULT_SPI_CFG[0]; + cpol <= DEFAULT_SPI_CFG[1]; + three_wire <= DEFAULT_SPI_CFG[2]; sdo_idle_state <= SDO_DEFAULT; - clk_div <= DEFAULT_CLK_DIV; - word_length <= DATA_WIDTH; - left_aligned <= 8'b0; - end else if (exec_write_cmd == 1'b1) begin - if (cmd[9:8] == REG_CONFIG) begin - cpha <= cmd[0]; - cpol <= cmd[1]; - three_wire <= cmd[2]; - sdo_idle_state <= cmd[3]; - end else if (cmd[9:8] == REG_CLK_DIV) begin - clk_div <= cmd[7:0]; - end else if (cmd[9:8] == REG_WORD_LENGTH) begin - // the max value of this reg must be DATA_WIDTH - word_length <= cmd[7:0]; - left_aligned <= DATA_WIDTH - cmd[7:0]; // needed 1 cycle before transfer_active goes high + clk_div <= DEFAULT_CLK_DIV; + word_length <= DATA_WIDTH; + left_aligned <= 0; + sdi_lane_mask <= ALL_ACTIVE_LANE_MASK; + sdo_lane_mask <= ALL_ACTIVE_LANE_MASK; + end else begin + if (exec_write_cmd) begin + case (cmd[10:8]) + REG_CLK_DIV : begin + clk_div <= cmd[7:0]; + end + REG_CONFIG : begin + cpha <= cmd[0]; + cpol <= cmd[1]; + three_wire <= cmd[2]; + sdo_idle_state <= cmd[3]; + end + REG_WORD_LENGTH : begin + // the max value of this reg must be DATA_WIDTH + word_length <= cmd[7:0]; + // needed 1 cycle before transfer_active goes high + left_aligned <= DATA_WIDTH - cmd[7:0]; + end + REG_SDI_LANE_CONFIG : begin + sdi_lane_mask <= cmd[7:0]; + end + REG_SDO_LANE_CONFIG : begin + //max number of spi lanes is 8 + sdo_lane_mask <= cmd[7:0]; + end + endcase end end end @@ -272,53 +319,50 @@ module spi_engine_execution #( end always @(posedge clk) begin - if ((clk_div_last == 1'b0 && idle == 1'b0 && wait_for_io == 1'b0 && - clk_div_counter == 'h01) || clk_div == 'h00) - clk_div_last <= 1'b1; - else - clk_div_last <= 1'b0; - end - - always @(posedge clk) begin - if (clk_div_last == 1'b1 || idle == 1'b1 || wait_for_io == 1'b1) begin + if (~|clk_div_counter || idle || wait_for_io) begin clk_div_counter <= clk_div; - trigger <= 1'b1; + trigger <= 1'b1; end else begin clk_div_counter <= clk_div_counter - 1'b1; - trigger <= 1'b0; + trigger <= 1'b0; end + clk_div_last <= ((~clk_div_last && ~idle && ~wait_for_io && clk_div_counter == 8'h1) || ~|clk_div); end - assign trigger_tx = trigger == 1'b1 && ntx_rx == 1'b0; - assign trigger_rx = trigger == 1'b1 && ntx_rx == 1'b1; - - assign sleep_counter_compare = sleep_counter == cmd_d1[7:0]+1; - assign cs_sleep_counter_compare = cs_sleep_counter == cmd_d1[9:8]; - assign cs_sleep_early_exit = (cmd_d1[9:8] == 2'b00); + assign trigger_tx = trigger && ~ntx_rx; + assign trigger_rx = trigger && ntx_rx; always @(posedge clk) begin - if (resetn == 1'b0) begin + if (!resetn) begin cs_sleep_repeat <= 1'b0; end else begin if (idle) begin cs_sleep_repeat <= 1'b0; - end else if (cs_sleep_counter_compare && (inst_d1 == CMD_CHIPSELECT)) begin + end else if (cs_sleep_counter_compare && exec_chipselect_cmd_reg) begin cs_sleep_repeat <= !cs_sleep_repeat; end end end always @(posedge clk) begin - if (idle == 1'b1) begin - bit_counter <= 'h0; - transfer_counter <= 'h0; + if (idle) begin + bit_counter <= 0; + first_bit <= 1'b1; + last_bit <= 1'b0; + transfer_counter <= 0; ntx_rx <= 1'b0; sleep_counter_increment <= 1'b0; - sleep_counter <= 'h0; + sleep_counter <= 0; + if (cmd_valid) begin + cs_sleep_counter_compare <= 1'b0; + end end else begin - if (clk_div_last == 1'b1 && wait_for_io == 1'b0) begin + first_bit <= ((bit_counter + ntx_rx == 0) || (bit_counter == word_length-1)); + last_bit <= (bit_counter == last_bit_count); + + if (clk_div_last && ~wait_for_io) begin if (last_bit && transfer_active && ntx_rx) begin - bit_counter <= 'h0; + bit_counter <= 0; transfer_counter <= transfer_counter + 1; ntx_rx <= ~ntx_rx; end else begin @@ -328,23 +372,25 @@ module spi_engine_execution #( end else begin sleep_counter_increment <= ~sleep_counter_increment; sleep_counter <= sleep_counter + sleep_counter_increment; + cs_sleep_counter_compare <= (sleep_counter[1:0] + sleep_counter_increment) == cmd_d1_delay; end end end - if (cs_sleep_counter_compare && !cs_sleep_repeat && inst_d1 == CMD_CHIPSELECT) begin + if (cs_sleep_counter_compare && !cs_sleep_repeat && exec_chipselect_cmd_reg) begin sleep_counter <= 'h0; + cs_sleep_counter_compare <= 1'b0; end end end always @(posedge clk) begin - if (resetn == 1'b0) begin + if (!resetn) begin idle <= 1'b1; end else begin if (exec_transfer_cmd || exec_chipselect_cmd || exec_misc_cmd) begin idle <= 1'b0; end else begin - case (inst_d1) + case (cmd_d1_instr) CMD_TRANSFER: begin if (transfer_done) idle <= 1'b1; @@ -354,7 +400,7 @@ module spi_engine_execution #( idle <= 1'b1; end CMD_MISC: begin - case (cmd_d1[8]) + case (cmd_d1_sleep_instr) MISC_SLEEP: begin if (sleep_counter_compare) idle <= 1'b1; @@ -371,17 +417,17 @@ module spi_engine_execution #( end always @(posedge clk ) begin - if (resetn == 1'b0) begin - cs_inv_mask_reg <= 'h0; + if (!resetn) begin + cs_inv_mask_reg <= 0; end else begin - if (exec_cs_inv_cmd == 1'b1) begin + if (exec_cs_inv_cmd) begin cs_inv_mask_reg <= cmd[NUM_OF_CS-1:0]; end end end always @(posedge clk) begin - if (resetn == 1'b0) begin + if (!resetn) begin cs <= 'hff; end else if (cs_gen) begin cs <= cmd_d1[NUM_OF_CS-1:0]^cs_inv_mask_reg[NUM_OF_CS-1:0]; @@ -389,12 +435,12 @@ module spi_engine_execution #( end always @(posedge clk) begin - if (resetn == 1'b0) begin + if (!resetn) begin sync_valid <= 1'b0; end else begin - if (exec_sync_cmd == 1'b1) begin + if (exec_sync_cmd) begin sync_valid <= 1'b1; - end else if (sync_ready == 1'b1) begin + end else if (sync_ready) begin sync_valid <= 1'b0; end end @@ -402,30 +448,27 @@ module spi_engine_execution #( assign sync = cmd_d1[7:0]; - assign io_ready1 = (sdi_data_valid == 1'b0 || sdi_data_ready == 1'b1) && - (sdo_enabled_io == 1'b0 || sdo_io_ready == 1'b1); - assign io_ready2 = (sdi_enabled == 1'b0 || sdi_data_ready == 1'b1) && - (sdo_enabled_io == 1'b0 || last_transfer == 1'b1 || sdo_io_ready == 1'b1); + assign io_ready1 = (~sdi_data_valid || sdi_data_ready) && + (~sdo_enabled_io || sdo_io_ready); + assign io_ready2 = (~sdi_enabled || sdi_data_ready) && + (~sdo_enabled_io || last_transfer || sdo_io_ready); always @(posedge clk) begin - if (idle == 1'b1) begin + if (idle) begin last_transfer <= 1'b0; - end else if (trigger_tx == 1'b1 && transfer_active == 1'b1) begin - if (transfer_counter == cmd_d1[7:0]) - last_transfer <= 1'b1; - else - last_transfer <= 1'b0; + end else if (trigger_tx && transfer_active) begin + last_transfer <= (transfer_counter == cmd_d1[7:0]); end end always @(posedge clk) begin - if (resetn == 1'b0 || idle == 1'b1) begin + if (!resetn || idle) begin echo_last_transfer <= 1'b0; end else begin - if (inst_d1 == CMD_TRANSFER && cmd_d1[7:0] == 0) begin + if (exec_transfer_cmd_reg && cmd_d1_time_is_zero) begin echo_last_transfer <= 1'b1; - end else if (echo_last_bit == 1'b1) begin - if (echo_transfer_counter +1 == cmd_d1[7:0]) begin + end else if (echo_last_bit) begin + if (echo_transfer_counter + 1 == cmd_d1[7:0]) begin echo_last_transfer <= 1'b1; end else begin echo_last_transfer <= 1'b0; @@ -435,49 +478,49 @@ module spi_engine_execution #( end always @(posedge clk ) begin - if (resetn == 1'b0 || idle == 1'b1) begin + if (!resetn || idle) begin echo_transfer_counter <= 0; end else begin - if (echo_last_bit == 1'b1) begin + if (echo_last_bit) begin echo_transfer_counter <= echo_transfer_counter + 1; end end end always @(posedge clk) begin - if (resetn == 1'b0) begin + if (!resetn) begin transfer_active <= 1'b0; wait_for_io <= 1'b0; end else begin - if (exec_transfer_cmd == 1'b1) begin - wait_for_io <= !io_ready1; + if (exec_transfer_cmd) begin + wait_for_io <= ~io_ready1; transfer_active <= io_ready1; - end else if (wait_for_io == 1'b1 && io_ready1 == 1'b1) begin + end else if (wait_for_io && io_ready1) begin wait_for_io <= 1'b0; - transfer_active <= !last_transfer; - end else if (transfer_active == 1'b1 && end_of_word == 1'b1) begin - if (last_transfer == 1'b1 || io_ready2 == 1'b0) + transfer_active <= ~last_transfer; + end else if (transfer_active && end_of_word) begin + if (last_transfer || ~io_ready2) transfer_active <= 1'b0; - if (io_ready2 == 1'b0) + if (~io_ready2) wait_for_io <= 1'b1; end end end always @(posedge clk ) begin - if (resetn == 1'b0) begin + if (!resetn) begin transfer_done <= 1'b0; end else begin - if (ECHO_SCLK) begin + if (ECHO_SCLK) begin transfer_done <= echo_last_bit && echo_last_transfer; - end else begin - transfer_done <= (wait_for_io && io_ready1 && last_transfer) || (!wait_for_io && transfer_active && end_of_word && last_transfer ); - end + end else begin + transfer_done <= (wait_for_io && io_ready1 && last_transfer) || (~wait_for_io && transfer_active && end_of_word && last_transfer); + end end end always @(posedge clk) begin - if (transfer_active == 1'b1 || wait_for_io == 1'b1) + if (transfer_active || wait_for_io) begin sdo_t_int <= ~sdo_enabled; end else begin @@ -496,11 +539,10 @@ module spi_engine_execution #( // end_of_word will signal the end of a transaction, pushing the command // stream execution to the next command. end_of_word in normal mode can be // generated using the global bit_counter - assign last_bit = (bit_counter == last_bit_count); - assign end_of_word = last_bit == 1'b1 && ntx_rx == 1'b1 && clk_div_last == 1'b1; + assign end_of_word = last_bit && ntx_rx && clk_div_last; always @(posedge clk) begin - if (transfer_active == 1'b1) begin + if (transfer_active) begin sclk_int <= cpol ^ cpha ^ ntx_rx; end else begin sclk_int <= cpol; diff --git a/library/spi_engine/spi_engine_execution/spi_engine_execution_hw.tcl b/library/spi_engine/spi_engine_execution/spi_engine_execution_hw.tcl index 85385a42a0c..505b089cd15 100644 --- a/library/spi_engine/spi_engine_execution/spi_engine_execution_hw.tcl +++ b/library/spi_engine/spi_engine_execution/spi_engine_execution_hw.tcl @@ -11,7 +11,8 @@ ad_ip_create spi_engine_execution {SPI Engine Execution} set_module_property ELABORATION_CALLBACK p_elaboration ad_ip_files spi_engine_execution [list\ spi_engine_execution.v \ - spi_engine_execution_shiftreg.v] + spi_engine_execution_shiftreg.v \ + spi_engine_execution_shiftreg_data_assemble.v] # parameters @@ -19,14 +20,14 @@ ad_ip_parameter NUM_OF_CS INTEGER 1 ad_ip_parameter DEFAULT_SPI_CFG INTEGER 0 ad_ip_parameter DEFAULT_CLK_DIV INTEGER 0 ad_ip_parameter DATA_WIDTH INTEGER 8 -ad_ip_parameter NUM_OF_SDI INTEGER 1 +ad_ip_parameter NUM_OF_SDIO INTEGER 1 ad_ip_parameter SDI_DELAY INTEGER 0 ad_ip_parameter SDO_DEFAULT INTEGER 0 proc p_elaboration {} { set data_width [get_parameter_value DATA_WIDTH] - set num_of_sdi [get_parameter_value NUM_OF_SDI] + set num_of_sdi [get_parameter_value NUM_OF_SDIO] set num_of_cs [get_parameter_value NUM_OF_CS] # clock and reset interface @@ -36,6 +37,13 @@ proc p_elaboration {} { ad_interface signal active output 1 + # interconnect direction interface + + add_interface s_interconnect_ctrl conduit end + add_interface_port s_interconnect_ctrl s_interconnect_dir interconnect_dir input 1 + set_interface_property s_interconnect_ctrl associatedClock if_clk + set_interface_property s_interconnect_ctrl associatedReset if_resetn + # command interface add_interface cmd axi4stream end diff --git a/library/spi_engine/spi_engine_execution/spi_engine_execution_ip.tcl b/library/spi_engine/spi_engine_execution/spi_engine_execution_ip.tcl index 5b625ae4a89..cc2cf59421b 100644 --- a/library/spi_engine/spi_engine_execution/spi_engine_execution_ip.tcl +++ b/library/spi_engine/spi_engine_execution/spi_engine_execution_ip.tcl @@ -11,6 +11,7 @@ adi_ip_files spi_engine_execution [list \ "spi_engine_execution_constr.ttcl" \ "spi_engine_execution.v" \ "spi_engine_execution_shiftreg.v" \ + "spi_engine_execution_shiftreg_data_assemble.v" \ ] adi_ip_properties_lite spi_engine_execution @@ -42,6 +43,14 @@ adi_add_bus "ctrl" "slave" \ } adi_add_bus_clock "clk" "ctrl" "resetn" +adi_add_bus "s_offload_active_ctrl" "slave" \ + "analog.com:interface:spi_engine_interconnect_ctrl_rtl:1.0" \ + "analog.com:interface:spi_engine_interconnect_ctrl:1.0" \ + { \ + {"s_offload_active" "interconnect_dir"} \ + } +adi_add_bus_clock "clk" "s_offload_active_ctrl" "resetn" + adi_add_bus "spi" "master" \ "analog.com:interface:spi_engine_rtl:1.0" \ "analog.com:interface:spi_engine:1.0" \ @@ -75,13 +84,13 @@ set_property -dict [list \ ] \ [ipx::get_user_parameters NUM_OF_CS -of_objects $cc] -## NUM_OF_SDI +## NUM_OF_SDIO set_property -dict [list \ "value_validation_type" "range_long" \ "value_validation_range_minimum" "1" \ "value_validation_range_maximum" "8" \ ] \ - [ipx::get_user_parameters NUM_OF_SDI -of_objects $cc] + [ipx::get_user_parameters NUM_OF_SDIO -of_objects $cc] ## DEFAULT_SPI_CFG set_property -dict [list \ @@ -157,11 +166,11 @@ set_property -dict [list \ "tooltip" "\[NUM_OF_CS\] Define the number of chip select lines" \ ] [ipgui::get_guiparamspec -name "NUM_OF_CS" -component $cc] -ipgui::add_param -name "NUM_OF_SDI" -component $cc -parent $general_group +ipgui::add_param -name "NUM_OF_SDIO" -component $cc -parent $general_group set_property -dict [list \ - "display_name" "Number of MISO lines" \ - "tooltip" "\[NUM_OF_SDI\] Define the number of MISO lines" \ -] [ipgui::get_guiparamspec -name "NUM_OF_SDI" -component $cc] + "display_name" "Number of MISO/MOSI lines" \ + "tooltip" "\[NUM_OF_SDIO\] Define the number of MISO/MOSI lines" \ +] [ipgui::get_guiparamspec -name "NUM_OF_SDIO" -component $cc] set spi_config_group [ipgui::add_group -name "SPI Configuration" -component $cc \ -parent $page0 -display_name "SPI Configuration" ] @@ -182,11 +191,11 @@ set_property -dict [list \ set mosi_miso_config_group [ipgui::add_group -name "MOSI/MISO Configuration" -component $cc \ -parent $page0 -display_name "MOSI/MISO Configuration" ] -ipgui::add_param -name "NUM_OF_SDI" -component $cc -parent $mosi_miso_config_group +ipgui::add_param -name "NUM_OF_SDIO" -component $cc -parent $mosi_miso_config_group set_property -dict [list \ - "display_name" "Number of MISO" \ - "tooltip" "\[NUM_OF_SDI\] Define the number of MISO lines" -] [ipgui::get_guiparamspec -name "NUM_OF_SDI" -component $cc] + "display_name" "Number of MISO/MOSI" \ + "tooltip" "\[NUM_OF_SDIO\] Define the number of MISO/MOSI lines" +] [ipgui::get_guiparamspec -name "NUM_OF_SDIO" -component $cc] ipgui::add_param -name "SDI_DELAY" -component $cc -parent $mosi_miso_config_group set_property -dict [list \ diff --git a/library/spi_engine/spi_engine_execution/spi_engine_execution_ltt.tcl b/library/spi_engine/spi_engine_execution/spi_engine_execution_ltt.tcl index a234d664da0..53497f4d373 100644 --- a/library/spi_engine/spi_engine_execution/spi_engine_execution_ltt.tcl +++ b/library/spi_engine/spi_engine_execution/spi_engine_execution_ltt.tcl @@ -85,11 +85,11 @@ set ip [ipl::set_parameter -ip $ip \ -group1 {General Configuration} \ -group2 Config] set ip [ipl::set_parameter -ip $ip \ - -id NUM_OF_SDI \ + -id NUM_OF_SDIO \ -type param \ -value_type int \ -conn_mod spi_engine_execution \ - -title {Number of MISO} \ + -title {Number of MISO/MOSI} \ -default 1 \ -output_formatter nostr \ -value_range {(1, 8)} \ diff --git a/library/spi_engine/spi_engine_execution/spi_engine_execution_shiftreg.v b/library/spi_engine/spi_engine_execution/spi_engine_execution_shiftreg.v index fd264a6423f..7220737fce9 100644 --- a/library/spi_engine/spi_engine_execution/spi_engine_execution_shiftreg.v +++ b/library/spi_engine/spi_engine_execution/spi_engine_execution_shiftreg.v @@ -38,26 +38,31 @@ module spi_engine_execution_shiftreg #( parameter DEFAULT_SPI_CFG = 0, + parameter ALL_ACTIVE_LANE_MASK = 8'hFF, parameter DATA_WIDTH = 8, - parameter NUM_OF_SDI = 1, + parameter NUM_OF_SDIO = 1, parameter [1:0] SDI_DELAY = 2'b00, parameter ECHO_SCLK = 0, - parameter [2:0]CMD_TRANSFER = 3'b000 + parameter [2:0] CMD_TRANSFER = 3'b000, + parameter [2:0] CMD_WRITE = 3'b010 ) ( input clk, input resetn, + //interconnect interface + input s_offload_active, + // spi io - input [NUM_OF_SDI-1:0] sdi, - output sdo_int, + input [NUM_OF_SDIO-1:0] sdi, + output [NUM_OF_SDIO-1:0] sdo_int, input echo_sclk, // spi data - input [(DATA_WIDTH-1):0] sdo_data, - input sdo_data_valid, - output sdo_data_ready, + input [(DATA_WIDTH)-1:0] sdo_data, + input sdo_data_valid, + output sdo_data_ready, - output [(NUM_OF_SDI * DATA_WIDTH-1):0] sdi_data, + output [(NUM_OF_SDIO * DATA_WIDTH)-1:0] sdi_data, output reg sdi_data_valid, input sdi_data_ready, @@ -65,9 +70,12 @@ module spi_engine_execution_shiftreg #( input sdo_enabled, input sdi_enabled, input [15:0] current_cmd, + input exec_cmd, + input exec_sdo_lane_cmd, input sdo_idle_state, input [ 7:0] left_aligned, input [ 7:0] word_length, + input [ 7:0] sdo_lane_mask, // timing from main fsm output sdo_io_ready, @@ -80,54 +88,69 @@ module spi_engine_execution_shiftreg #( ); reg [ 7:0] sdi_counter = 8'b0; - reg [(DATA_WIDTH-1):0] data_sdo_shift = 'h0; reg [ SDI_DELAY+1:0] trigger_rx_d = {(SDI_DELAY+2){1'b0}}; - reg [(DATA_WIDTH-1):0] aligned_sdo_data, sdo_data_reg; - reg data_sdo_v; - wire sdo_toshiftreg; + wire data_sdo_v; //data_sdo_v == existence of valid data + wire sdo_toshiftreg; //it is using the valid data for shifting in this cycle wire last_sdi_bit; wire trigger_rx_s; - wire [2:0] current_instr = current_cmd[14:12]; - - // sdo data handshake - assign sdo_data_ready = (!data_sdo_v) || sdo_toshiftreg; + wire index_ready; + wire sdo_data_ready_int; + + // sdo_data_ready_int is active when two conditions are true: + // ((!data_sdo_v) || (sdo_toshiftreg)) + // there's room for storing sdo data + // AND + // (s_offload_active || current_instr == CMD_TRANSFER) + // when s_offload_active, it is possible to prefetch + // when !s_offload_active, it is waiting for write instruction + assign sdo_data_ready_int = ((!data_sdo_v) || (sdo_toshiftreg)) && (s_offload_active || (exec_cmd & index_ready)); + assign sdo_data_ready = sdo_data_ready_int; assign sdo_io_ready = data_sdo_v; - always @(posedge clk ) begin - if (resetn == 1'b0) begin - data_sdo_v <= 1'b0; - end else begin - if (sdo_data_ready && sdo_data_valid) begin - data_sdo_v <= 1'b1; - sdo_data_reg <= sdo_data; - end else if (sdo_toshiftreg) begin - data_sdo_v <= 1'b0; - end - end - end - // pipelined shifter for sdo_data - always @(posedge clk ) begin - if (resetn == 1'b0) begin - aligned_sdo_data <= 0; - end else begin - aligned_sdo_data <= sdo_data_reg << left_aligned; - end - end + wire [(NUM_OF_SDIO * DATA_WIDTH)-1:0] aligned_sdo_data; + spi_engine_execution_shiftreg_data_assemble #( + .ALL_ACTIVE_LANE_MASK(ALL_ACTIVE_LANE_MASK), + .DATA_WIDTH(DATA_WIDTH), + .NUM_OF_SDIO(NUM_OF_SDIO), + .CMD_WRITE(CMD_WRITE) + ) sdo_data_assemble ( + .clk (clk), + .resetn (resetn), + .data (sdo_data), + .data_ready (sdo_data_ready_int), + .data_valid (sdo_data_valid), + .current_cmd (current_cmd), + .exec_sdo_lane_cmd(exec_sdo_lane_cmd), + .lane_mask (sdo_lane_mask), + .idle_state (sdo_idle_state), + .left_aligned (left_aligned), + .transfer_active (transfer_active), + .trigger_tx (trigger_tx), + .first_bit (first_bit), + .sdo_enabled (sdo_enabled), + .index_ready (index_ready), + .data_assembled (aligned_sdo_data), + .last_handshake (data_sdo_v)); - // Load the SDO parallel data into the SDO shift register. In case of a custom - // data width, additional bit shifting must done at load. - always @(posedge clk) begin - if (!sdo_enabled || (current_instr != CMD_TRANSFER)) begin - data_sdo_shift <= {DATA_WIDTH{sdo_idle_state}}; - end else if (transfer_active == 1'b1 && trigger_tx == 1'b1) begin - if (first_bit == 1'b1) begin - data_sdo_shift <= aligned_sdo_data; - end else begin - data_sdo_shift <= {data_sdo_shift[(DATA_WIDTH-2):0], 1'b0}; + genvar i; + for (i = 0; i < NUM_OF_SDIO; i = i + 1) begin: g_sdo_shift_reg + // Load the SDO parallel data into the SDO shift register. + reg [(DATA_WIDTH-1):0] data_sdo_shift = 'h0; + always @(posedge clk) begin + if (!sdo_enabled || !exec_cmd) begin + data_sdo_shift <= {DATA_WIDTH{sdo_idle_state}}; + end else if (transfer_active == 1'b1 && trigger_tx == 1'b1) begin + if (first_bit == 1'b1) begin + data_sdo_shift <= sdo_lane_mask[i] ? aligned_sdo_data[i * DATA_WIDTH+:DATA_WIDTH] : {DATA_WIDTH{sdo_idle_state}}; + end else begin + data_sdo_shift <= {data_sdo_shift[(DATA_WIDTH-2):0], 1'b0}; + end end end + + assign sdo_int[i] = data_sdo_shift[DATA_WIDTH-1]; end - assign sdo_int = data_sdo_shift[DATA_WIDTH-1]; + assign sdo_toshiftreg = (transfer_active && trigger_tx && first_bit && sdo_enabled); // In case of an interface with high clock rate (SCLK > 50MHz), the latch of @@ -149,19 +172,18 @@ module spi_engine_execution_shiftreg #( // used to latch the MISO lines, improving the overall timing margin of the // interface. - genvar i; // NOTE: SPI configuration (CPOL/PHA) is only hardware configurable at this point, unless ECHO_SCLK=0 generate if (ECHO_SCLK == 1) begin : g_echo_sclk_miso_latch reg last_sdi_bit_r; reg latch_sdi; - reg [(NUM_OF_SDI * DATA_WIDTH)-1:0] sdi_data_latch = {(NUM_OF_SDI * DATA_WIDTH){1'b0}}; + reg [(NUM_OF_SDIO * DATA_WIDTH)-1:0] sdi_data_latch = {(NUM_OF_SDIO * DATA_WIDTH){1'b0}}; if ((DEFAULT_SPI_CFG[1:0] == 2'b01) || (DEFAULT_SPI_CFG[1:0] == 2'b10)) begin : g_echo_miso_nshift_reg // MISO shift register runs on negative echo_sclk - for (i=0; i +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module spi_engine_execution_shiftreg_data_assemble #( + + parameter ALL_ACTIVE_LANE_MASK = 8'hFF, + parameter DATA_WIDTH = 8, + parameter NUM_OF_SDIO = 1, + parameter [2:0] CMD_WRITE = 3'b010 +) ( + input clk, + input resetn, + input [(DATA_WIDTH)-1:0] data, + input data_ready, + input data_valid, + input [15:0] current_cmd, + input exec_sdo_lane_cmd, + input [7:0] lane_mask, + input idle_state, + input [7:0] left_aligned, + input transfer_active, + input trigger_tx, + input first_bit, + input sdo_enabled, + output index_ready, + output [(NUM_OF_SDIO * DATA_WIDTH)-1:0] data_assembled, + output last_handshake +); + + // This module is responsible to align data for different lane masks + // if lane_mask has all of its SDOs activated, then it allows prefetch data + // if not, non activated serial lines have their data fulfilled with idle_state and buffer the remaining activated lines + // also, in this mode it is not possible to prefetch data + + reg last_handshake_int; + reg [(NUM_OF_SDIO * DATA_WIDTH)-1:0] aligned_data; + reg [ (DATA_WIDTH)-1:0] data_reg; + reg [ 3:0] count_active_lanes = 0; + reg [ 3:0] num_active_lanes = NUM_OF_SDIO; + reg [ 3:0] lane_index = 0; + reg [ 3:0] lane_index_d = 0; + reg [ 3:0] valid_indices [0:7]; + + wire sdo_toshiftreg = (transfer_active && trigger_tx && first_bit && sdo_enabled); + integer valid_index = 0; + + assign data_assembled = aligned_data; + assign last_handshake = last_handshake_int; + assign index_ready = index_ready_reg; + + // register data + always @(posedge clk) begin + if (resetn == 1'b0) begin + data_reg <= {DATA_WIDTH{idle_state}}; + end else begin + if (data_ready && data_valid) begin + data_reg <= data; + end + end + end + + // Align data to have its bits on the MSB bits + // data is left shifted left_aligned times, where left_aligned equals to DATA_WIDTH - word_length + // word_length comes from the dynamic transfer length register + always @(posedge clk) begin + if (resetn == 1'b0) begin + aligned_data <= {(NUM_OF_SDIO * DATA_WIDTH){idle_state}}; + end else begin + aligned_data[valid_index * DATA_WIDTH+:DATA_WIDTH] <= data_reg << left_aligned; + end + end + + // data line counter and stores activated lines + // it returns valid_indices array necessary for correct buffering of data + reg [3:0] i; + reg [3:0] j; + reg [3:0] mask_index; + reg index_ready_reg; + always @(posedge clk) begin + if (resetn == 1'b0) begin + num_active_lanes <= NUM_OF_SDIO; + index_ready_reg <= 1'b0; + mask_index <= 0; + j <= 0; + end else begin + if (exec_sdo_lane_cmd) begin + count_active_lanes = 0; + i = 0; + j <= 0; + index_ready_reg <= 1'b0; + mask_index <= 0; + for (i = 0; i < NUM_OF_SDIO; i = i + 1) begin + count_active_lanes = count_active_lanes + current_cmd[i]; + end + num_active_lanes <= count_active_lanes; + end else begin + if (j < NUM_OF_SDIO) begin + if (lane_mask[j]) begin + valid_indices[mask_index] <= j; + mask_index <= mask_index + 1; + end + j <= j + 1; + index_ready_reg <= (j == NUM_OF_SDIO-1) ? 1'b1 : 1'b0; + end + end + end + end + + // handshake counter + // it will increment up to num_active_lanes + // The last handshake is used by external logic to enable sdo_io_ready + // retrieves the correct lane_index used to align data + always @(posedge clk) begin + if (resetn == 1'b0) begin + lane_index <= 0; + lane_index_d <= 0; + valid_index <= 0; + last_handshake_int <= 1'b0; + end else begin + if (data_ready && data_valid) begin + last_handshake_int <= (lane_index == (num_active_lanes-1)) ? 1'b1 : 1'b0; + if (lane_index < (num_active_lanes-1)) begin + lane_index <= lane_index + 1; + end else begin + lane_index <= 0; + end + lane_index_d <= lane_index; + valid_index <= (lane_mask == ALL_ACTIVE_LANE_MASK) ? lane_index : valid_indices[lane_index_d]; + end else if (sdo_toshiftreg) begin + last_handshake_int <= 1'b0; + end + end + end + + endmodule diff --git a/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v b/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v index 9fe18eac282..ff1ecc3a9d2 100644 --- a/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v +++ b/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v @@ -38,12 +38,13 @@ module spi_engine_interconnect #( parameter DATA_WIDTH = 8, // Valid data widths values are 8/16/24/32 - parameter NUM_OF_SDI = 1 + parameter NUM_OF_SDIO = 1 ) ( input clk, input resetn, - input interconnect_dir, + input s_interconnect_dir, + output m_offload_active, output m_cmd_valid, input m_cmd_ready, @@ -55,7 +56,7 @@ module spi_engine_interconnect #( input m_sdi_valid, output m_sdi_ready, - input [(NUM_OF_SDI * DATA_WIDTH-1):0] m_sdi_data, + input [(NUM_OF_SDIO * DATA_WIDTH-1):0] m_sdi_data, input m_sync_valid, output m_sync_ready, @@ -71,7 +72,7 @@ module spi_engine_interconnect #( output s0_sdi_valid, input s0_sdi_ready, - output [(NUM_OF_SDI * DATA_WIDTH-1):0] s0_sdi_data, + output [(NUM_OF_SDIO * DATA_WIDTH-1):0] s0_sdi_data, output s0_sync_valid, input s0_sync_ready, @@ -87,15 +88,16 @@ module spi_engine_interconnect #( output s1_sdi_valid, input s1_sdi_ready, - output [(NUM_OF_SDI * DATA_WIDTH-1):0] s1_sdi_data, + output [(NUM_OF_SDIO * DATA_WIDTH-1):0] s1_sdi_data, output s1_sync_valid, input s1_sync_ready, output [7:0] s1_sync ); - `define spi_engine_interconnect_mux(s0, s1) (interconnect_dir == 1'b1 ? s0 : s1) + `define spi_engine_interconnect_mux(s0, s1) (s_interconnect_dir == 1'b1 ? s0 : s1) + assign m_offload_active = s_interconnect_dir; assign m_cmd_data = `spi_engine_interconnect_mux(s0_cmd_data, s1_cmd_data); assign m_cmd_valid = `spi_engine_interconnect_mux(s0_cmd_valid, s1_cmd_valid); assign s0_cmd_ready = `spi_engine_interconnect_mux(m_cmd_ready, 1'b0); diff --git a/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect_hw.tcl b/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect_hw.tcl index a64057fee69..bb69d4fd2cc 100644 --- a/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect_hw.tcl +++ b/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect_hw.tcl @@ -14,12 +14,12 @@ ad_ip_files spi_engine_interconnect [list\ # parameters ad_ip_parameter DATA_WIDTH INTEGER 8 -ad_ip_parameter NUM_OF_SDI INTEGER 1 +ad_ip_parameter NUM_OF_SDIO INTEGER 1 proc p_elaboration {} { set data_width [get_parameter_value DATA_WIDTH] - set num_of_sdi [get_parameter_value NUM_OF_SDI] + set num_of_sdi [get_parameter_value NUM_OF_SDIO] # clock and reset interface @@ -29,7 +29,7 @@ proc p_elaboration {} { # interconnect direction interface add_interface s_interconnect_ctrl conduit end - add_interface_port s_interconnect_ctrl interconnect_dir interconnect_dir input 1 + add_interface_port s_interconnect_ctrl s_interconnect_dir interconnect_dir input 1 set_interface_property s_interconnect_ctrl associatedClock if_clk set_interface_property s_interconnect_ctrl associatedReset if_resetn diff --git a/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect_ip.tcl b/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect_ip.tcl index 79710328e08..2c99a636a5f 100644 --- a/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect_ip.tcl +++ b/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect_ip.tcl @@ -43,10 +43,18 @@ adi_add_bus "s_interconnect_ctrl" "slave" \ "analog.com:interface:spi_engine_interconnect_ctrl_rtl:1.0" \ "analog.com:interface:spi_engine_interconnect_ctrl:1.0" \ { \ - {"interconnect_dir" "interconnect_dir"} \ + {"s_interconnect_dir" "interconnect_dir"} \ } adi_add_bus_clock "clk" "s_interconnect_ctrl" "resetn" +adi_add_bus "m_offload_active_ctrl" "master" \ + "analog.com:interface:spi_engine_interconnect_ctrl_rtl:1.0" \ + "analog.com:interface:spi_engine_interconnect_ctrl:1.0" \ + { \ + {"m_offload_active" "interconnect_dir"} \ + } +adi_add_bus_clock "clk" "m_offload_active_ctrl" "resetn" + foreach prefix [list "s0" "s1"] { adi_add_bus [format "%s_ctrl" $prefix] "slave" \ "analog.com:interface:spi_engine_ctrl_rtl:1.0" \ @@ -80,13 +88,13 @@ set_property -dict [list \ ] \ [ipx::get_user_parameters DATA_WIDTH -of_objects $cc] -## NUM_OF_SDI +## NUM_OF_SDIO set_property -dict [list \ "value_validation_type" "range_long" \ "value_validation_range_minimum" "1" \ "value_validation_range_maximum" "8" \ ] \ - [ipx::get_user_parameters NUM_OF_SDI -of_objects $cc] + [ipx::get_user_parameters NUM_OF_SDIO -of_objects $cc] ## Customize IP Layout @@ -107,11 +115,11 @@ set_property -dict [list \ "tooltip" "\[DATA_WIDTH\] Define the data interface width" ] [ipgui::get_guiparamspec -name "DATA_WIDTH" -component $cc] -ipgui::add_param -name "NUM_OF_SDI" -component $cc -parent $general_group +ipgui::add_param -name "NUM_OF_SDIO" -component $cc -parent $general_group set_property -dict [list \ - "display_name" "Number of MISO lines" \ - "tooltip" "\[NUM_OF_SDI\] Define the number of MISO lines" \ -] [ipgui::get_guiparamspec -name "NUM_OF_SDI" -component $cc] + "display_name" "Number of MISO/MOSI lines" \ + "tooltip" "\[NUM_OF_SDIO\] Define the number of MISO/MOSI lines" \ +] [ipgui::get_guiparamspec -name "NUM_OF_SDIO" -component $cc] ## Create and save the XGUI file ipx::create_xgui_files $cc diff --git a/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect_ltt.tcl b/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect_ltt.tcl index 70c0cd3ed51..6674a97c0e0 100755 --- a/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect_ltt.tcl +++ b/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect_ltt.tcl @@ -82,11 +82,11 @@ set ip [ipl::set_parameter -ip $ip \ -group1 {General Configuration} \ -group2 Config] set ip [ipl::set_parameter -ip $ip \ - -id NUM_OF_SDI \ + -id NUM_OF_SDIO \ -type param \ -value_type int \ -conn_mod spi_engine_interconnect \ - -title {Number of MISO lines} \ + -title {Number of MISO/MOSI lines} \ -default 1 \ -output_formatter nostr \ -value_range {(1, 8)} \ diff --git a/library/spi_engine/spi_engine_offload/spi_engine_offload.v b/library/spi_engine/spi_engine_offload/spi_engine_offload.v index 329984b41f2..dc567c3c7b7 100644 --- a/library/spi_engine/spi_engine_offload/spi_engine_offload.v +++ b/library/spi_engine/spi_engine_offload/spi_engine_offload.v @@ -42,7 +42,7 @@ module spi_engine_offload #( parameter CMD_MEM_ADDRESS_WIDTH = 4, parameter SDO_MEM_ADDRESS_WIDTH = 4, parameter DATA_WIDTH = 8, // Valid data widths values are 8/16/24/32 - parameter NUM_OF_SDI = 1, + parameter NUM_OF_SDIO = 1, parameter SDO_STREAMING = 0 ) ( input ctrl_clk, @@ -80,7 +80,7 @@ module spi_engine_offload #( input sdi_data_valid, output sdi_data_ready, - input [(NUM_OF_SDI * DATA_WIDTH-1):0] sdi_data, + input [(NUM_OF_SDIO * DATA_WIDTH)-1:0] sdi_data, input sync_valid, output sync_ready, @@ -88,7 +88,7 @@ module spi_engine_offload #( output offload_sdi_valid, input offload_sdi_ready, - output [(NUM_OF_SDI * DATA_WIDTH-1):0] offload_sdi_data, + output [(NUM_OF_SDIO * DATA_WIDTH)-1:0] offload_sdi_data, output interconnect_dir ); diff --git a/library/spi_engine/spi_engine_offload/spi_engine_offload_hw.tcl b/library/spi_engine/spi_engine_offload/spi_engine_offload_hw.tcl index 86fb0008b83..5fe52738d4c 100644 --- a/library/spi_engine/spi_engine_offload/spi_engine_offload_hw.tcl +++ b/library/spi_engine/spi_engine_offload/spi_engine_offload_hw.tcl @@ -20,13 +20,13 @@ ad_ip_parameter ASYNC_TRIG INTEGER 0 ad_ip_parameter CMD_MEM_ADDRESS_WIDTH INTEGER 4 ad_ip_parameter SDO_MEM_ADDRESS_WIDTH INTEGER 4 ad_ip_parameter DATA_WIDTH INTEGER 8 -ad_ip_parameter NUM_OF_SDI INTEGER 1 +ad_ip_parameter NUM_OF_SDIO INTEGER 1 ad_ip_parameter SDO_STREAMING INTEGER 0 proc p_elaboration {} { set data_width [get_parameter_value DATA_WIDTH] - set num_of_sdi [get_parameter_value NUM_OF_SDI] + set num_of_sdi [get_parameter_value NUM_OF_SDIO] set disabled_intfs {} # control interface diff --git a/library/spi_engine/spi_engine_offload/spi_engine_offload_ip.tcl b/library/spi_engine/spi_engine_offload/spi_engine_offload_ip.tcl index f7abbeaf173..4b3c358d159 100644 --- a/library/spi_engine/spi_engine_offload/spi_engine_offload_ip.tcl +++ b/library/spi_engine/spi_engine_offload/spi_engine_offload_ip.tcl @@ -132,13 +132,13 @@ set_property -dict [list \ ] \ [ipx::get_hdl_parameters SDO_STREAMING -of_objects $cc] -## NUM_OF_SDI +## NUM_OF_SDIO set_property -dict [list \ "value_validation_type" "range_long" \ "value_validation_range_minimum" "1" \ "value_validation_range_maximum" "8" \ ] \ - [ipx::get_user_parameters NUM_OF_SDI -of_objects $cc] + [ipx::get_user_parameters NUM_OF_SDIO -of_objects $cc] ## DATA_WIDTH set_property -dict [list \ @@ -183,11 +183,11 @@ set_property -dict [list \ "tooltip" "\[DATA_WIDTH\] Define the data interface width" ] [ipgui::get_guiparamspec -name "DATA_WIDTH" -component $cc] -ipgui::add_param -name "NUM_OF_SDI" -component $cc -parent $general_group +ipgui::add_param -name "NUM_OF_SDIO" -component $cc -parent $general_group set_property -dict [list \ - "display_name" "Number of MISO lines" \ - "tooltip" "\[NUM_OF_SDI\] Define the number of MISO lines" \ -] [ipgui::get_guiparamspec -name "NUM_OF_SDI" -component $cc] + "display_name" "Number of MISO/MOSI lines" \ + "tooltip" "\[NUM_OF_SDIO\] Define the number of MISO/MOSI lines" \ +] [ipgui::get_guiparamspec -name "NUM_OF_SDIO" -component $cc] ipgui::add_param -name "ASYNC_SPI_CLK" -component $cc -parent $general_group set_property -dict [list \ diff --git a/library/spi_engine/spi_engine_offload/spi_engine_offload_ltt.tcl b/library/spi_engine/spi_engine_offload/spi_engine_offload_ltt.tcl index 59e4d372bac..e416b8d00ed 100755 --- a/library/spi_engine/spi_engine_offload/spi_engine_offload_ltt.tcl +++ b/library/spi_engine/spi_engine_offload/spi_engine_offload_ltt.tcl @@ -103,11 +103,11 @@ set ip [ipl::set_parameter -ip $ip \ -group1 {General Configuration} \ -group2 Config] set ip [ipl::set_parameter -ip $ip \ - -id NUM_OF_SDI \ + -id NUM_OF_SDIO \ -type param \ -value_type int \ -conn_mod spi_engine_offload \ - -title {Number of MISO lines} \ + -title {Number of MISO/MOSI lines} \ -default 1 \ -output_formatter nostr \ -value_range {(1, 8)} \ diff --git a/projects/ad4052_ardz/common/ad4052_qsys.tcl b/projects/ad4052_ardz/common/ad4052_qsys.tcl index 8fcfd726de8..f8373d13ece 100644 --- a/projects/ad4052_ardz/common/ad4052_qsys.tcl +++ b/projects/ad4052_ardz/common/ad4052_qsys.tcl @@ -17,21 +17,21 @@ add_instance axi_spi_engine_0 axi_spi_engine set_instance_parameter_value axi_spi_engine_0 {ASYNC_SPI_CLK} {1} set_instance_parameter_value axi_spi_engine_0 {DATA_WIDTH} {32} set_instance_parameter_value axi_spi_engine_0 {MM_IF_TYPE} {0} -set_instance_parameter_value axi_spi_engine_0 {NUM_OF_SDI} {1} +set_instance_parameter_value axi_spi_engine_0 {NUM_OF_SDIO} {1} set_instance_parameter_value axi_spi_engine_0 {NUM_OFFLOAD} {1} # spi_engine_execution add_instance spi_engine_execution_0 spi_engine_execution set_instance_parameter_value spi_engine_execution_0 {DATA_WIDTH} {32} -set_instance_parameter_value spi_engine_execution_0 {NUM_OF_SDI} {1} +set_instance_parameter_value spi_engine_execution_0 {NUM_OF_SDIO} {1} set_instance_parameter_value spi_engine_execution_0 {SDI_DELAY} {0} # spi_engine_interconnect add_instance spi_engine_interconnect_0 spi_engine_interconnect set_instance_parameter_value spi_engine_interconnect_0 {DATA_WIDTH} {32} -set_instance_parameter_value spi_engine_interconnect_0 {NUM_OF_SDI} {1} +set_instance_parameter_value spi_engine_interconnect_0 {NUM_OF_SDIO} {1} # spi_engine_offload @@ -39,7 +39,7 @@ add_instance spi_engine_offload_0 spi_engine_offload set_instance_parameter_value spi_engine_offload_0 {ASYNC_TRIG} {1} set_instance_parameter_value spi_engine_offload_0 {ASYNC_SPI_CLK} {0} set_instance_parameter_value spi_engine_offload_0 {DATA_WIDTH} {32} -set_instance_parameter_value spi_engine_offload_0 {NUM_OF_SDI} {1} +set_instance_parameter_value spi_engine_offload_0 {NUM_OF_SDIO} {1} # axi_pwm_gen diff --git a/projects/ad411x_ad717x/common/ad411x_ad717x_asdz_qsys.tcl b/projects/ad411x_ad717x/common/ad411x_ad717x_asdz_qsys.tcl index db6df8bfb4a..06befcfba82 100644 --- a/projects/ad411x_ad717x/common/ad411x_ad717x_asdz_qsys.tcl +++ b/projects/ad411x_ad717x/common/ad411x_ad717x_asdz_qsys.tcl @@ -18,21 +18,21 @@ add_instance axi_spi_engine_0 axi_spi_engine set_instance_parameter_value axi_spi_engine_0 {ASYNC_SPI_CLK} {1} set_instance_parameter_value axi_spi_engine_0 {DATA_WIDTH} {32} set_instance_parameter_value axi_spi_engine_0 {MM_IF_TYPE} {0} -set_instance_parameter_value axi_spi_engine_0 {NUM_OF_SDI} {1} +set_instance_parameter_value axi_spi_engine_0 {NUM_OF_SDIO} {1} set_instance_parameter_value axi_spi_engine_0 {NUM_OFFLOAD} {1} # spi_engine_execution add_instance spi_engine_execution_0 spi_engine_execution set_instance_parameter_value spi_engine_execution_0 {DATA_WIDTH} {32} -set_instance_parameter_value spi_engine_execution_0 {NUM_OF_SDI} {1} +set_instance_parameter_value spi_engine_execution_0 {NUM_OF_SDIO} {1} set_instance_parameter_value spi_engine_execution_0 {SDI_DELAY} {0} # spi_engine_interconnect add_instance spi_engine_interconnect_0 spi_engine_interconnect set_instance_parameter_value spi_engine_interconnect_0 {DATA_WIDTH} {32} -set_instance_parameter_value spi_engine_interconnect_0 {NUM_OF_SDI} {1} +set_instance_parameter_value spi_engine_interconnect_0 {NUM_OF_SDIO} {1} # spi_engine_offload @@ -40,7 +40,7 @@ add_instance spi_engine_offload_0 spi_engine_offload set_instance_parameter_value spi_engine_offload_0 {ASYNC_TRIG} {1} set_instance_parameter_value spi_engine_offload_0 {ASYNC_SPI_CLK} {0} set_instance_parameter_value spi_engine_offload_0 {DATA_WIDTH} {32} -set_instance_parameter_value spi_engine_offload_0 {NUM_OF_SDI} {1} +set_instance_parameter_value spi_engine_offload_0 {NUM_OF_SDIO} {1} # util_sigma_delta_spi diff --git a/projects/ad4170_asdz/common/ad4170_asdz_qsys.tcl b/projects/ad4170_asdz/common/ad4170_asdz_qsys.tcl index a3930001aec..160bd86df52 100644 --- a/projects/ad4170_asdz/common/ad4170_asdz_qsys.tcl +++ b/projects/ad4170_asdz/common/ad4170_asdz_qsys.tcl @@ -19,21 +19,21 @@ add_instance axi_spi_engine_0 axi_spi_engine set_instance_parameter_value axi_spi_engine_0 {ASYNC_SPI_CLK} {1} set_instance_parameter_value axi_spi_engine_0 {DATA_WIDTH} {32} set_instance_parameter_value axi_spi_engine_0 {MM_IF_TYPE} {0} -set_instance_parameter_value axi_spi_engine_0 {NUM_OF_SDI} {1} +set_instance_parameter_value axi_spi_engine_0 {NUM_OF_SDIO} {1} set_instance_parameter_value axi_spi_engine_0 {NUM_OFFLOAD} {1} # spi_engine_execution add_instance spi_engine_execution_0 spi_engine_execution set_instance_parameter_value spi_engine_execution_0 {DATA_WIDTH} {32} -set_instance_parameter_value spi_engine_execution_0 {NUM_OF_SDI} {1} +set_instance_parameter_value spi_engine_execution_0 {NUM_OF_SDIO} {1} set_instance_parameter_value spi_engine_execution_0 {SDI_DELAY} {0} # spi_engine_interconnect add_instance spi_engine_interconnect_0 spi_engine_interconnect set_instance_parameter_value spi_engine_interconnect_0 {DATA_WIDTH} {32} -set_instance_parameter_value spi_engine_interconnect_0 {NUM_OF_SDI} {1} +set_instance_parameter_value spi_engine_interconnect_0 {NUM_OF_SDIO} {1} # bridges @@ -53,7 +53,7 @@ add_instance spi_engine_offload_0 spi_engine_offload set_instance_parameter_value spi_engine_offload_0 {ASYNC_TRIG} {1} set_instance_parameter_value spi_engine_offload_0 {ASYNC_SPI_CLK} {0} set_instance_parameter_value spi_engine_offload_0 {DATA_WIDTH} {32} -set_instance_parameter_value spi_engine_offload_0 {NUM_OF_SDI} {1} +set_instance_parameter_value spi_engine_offload_0 {NUM_OF_SDIO} {1} # exported interface diff --git a/projects/ad4630_fmc/common/ad463x_bd.tcl b/projects/ad4630_fmc/common/ad463x_bd.tcl index 0be531bfbc3..0c9f9f5fbbf 100644 --- a/projects/ad4630_fmc/common/ad463x_bd.tcl +++ b/projects/ad4630_fmc/common/ad463x_bd.tcl @@ -5,13 +5,13 @@ source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl # system level parameters -set NUM_OF_SDI $ad_project_params(NUM_OF_SDI) +set NUM_OF_SDIO $ad_project_params(NUM_OF_SDIO) set CAPTURE_ZONE $ad_project_params(CAPTURE_ZONE) set CLK_MODE $ad_project_params(CLK_MODE) set DDR_EN $ad_project_params(DDR_EN) set NO_REORDER $ad_project_params(NO_REORDER) -puts "build parameters: NUM_OF_SDI: $NUM_OF_SDI ; CAPTURE_ZONE: $CAPTURE_ZONE ; CLK_MODE: $CLK_MODE ; DDR_EN: $DDR_EN ; NO_REORDER: $NO_REORDER" +puts "build parameters: NUM_OF_SDIO: $NUM_OF_SDIO ; CAPTURE_ZONE: $CAPTURE_ZONE ; CLK_MODE: $CLK_MODE ; DDR_EN: $DDR_EN ; NO_REORDER: $NO_REORDER" # block design ports and interfaces # specify the CNV generator's reference clock frequency in MHz @@ -30,7 +30,7 @@ set max17687_sync_freq 400000 create_bd_port -dir O ad463x_spi_sclk create_bd_port -dir O ad463x_spi_cs create_bd_port -dir O ad463x_spi_sdo -create_bd_port -dir I -from [expr $NUM_OF_SDI-1] -to 0 ad463x_spi_sdi +create_bd_port -dir I -from [expr $NUM_OF_SDIO-1] -to 0 ad463x_spi_sdi create_bd_port -dir I ad463x_echo_sclk @@ -51,12 +51,12 @@ ad_connect spi_clk spi_clkgen/clk_0 # create a SPI Engine architecture -#spi_engine_create "spi_ad463x" 32 1 1 $NUM_OF_SDI 0 1 +#spi_engine_create "spi_ad463x" 32 1 1 $NUM_OF_SDIO 0 1 set data_width 32 set async_spi_clk 1 set num_cs 1 -set num_sdi $NUM_OF_SDI +set num_sdi $NUM_OF_SDIO set num_sdo 1 set sdi_delay 1 set echo_sclk 1 @@ -67,7 +67,7 @@ spi_engine_create $hier_spi_engine $data_width $async_spi_clk $num_cs $num_sdi $ ad_ip_parameter $hier_spi_engine/${hier_spi_engine}_execution CONFIG.DEFAULT_SPI_CFG 1 ; # latching MISO on negative edge - hardware only -ad_ip_parameter $hier_spi_engine/${hier_spi_engine}_axi_regmap CONFIG.CFG_INFO_0 $NUM_OF_SDI +ad_ip_parameter $hier_spi_engine/${hier_spi_engine}_axi_regmap CONFIG.CFG_INFO_0 $NUM_OF_SDIO ad_ip_parameter $hier_spi_engine/${hier_spi_engine}_axi_regmap CONFIG.CFG_INFO_1 $CAPTURE_ZONE ad_ip_parameter $hier_spi_engine/${hier_spi_engine}_axi_regmap CONFIG.CFG_INFO_2 $CLK_MODE ad_ip_parameter $hier_spi_engine/${hier_spi_engine}_axi_regmap CONFIG.CFG_INFO_3 $DDR_EN @@ -94,8 +94,17 @@ ad_ip_parameter sync_generator CONFIG.PULSE_0_WIDTH [expr int(ceil(double($max17 if {$NO_REORDER == 0} { - ad_ip_instance spi_axis_reorder data_reorder - ad_ip_parameter data_reorder CONFIG.NUM_OF_LANES $NUM_OF_SDI +ad_ip_instance spi_axis_reorder data_reorder +ad_ip_parameter data_reorder CONFIG.NUM_OF_LANES $NUM_OF_SDIO + +} elseif {$NO_REORDER == 1} { + + if {$CAPTURE_ZONE == 2} { + puts "ERROR: Invalid configuration - Disabling Reorder IP is invalid for Capture Zone 2." + exit 2 + } + +} } elseif {$NO_REORDER == 1} { @@ -186,7 +195,7 @@ if {$CAPTURE_ZONE == 1} { ## SDI is latched by the data capture ad_ip_instance ad463x_data_capture data_capture ad_ip_parameter data_capture CONFIG.DDR_EN $DDR_EN - ad_ip_parameter data_capture CONFIG.NUM_OF_LANES $NUM_OF_SDI + ad_ip_parameter data_capture CONFIG.NUM_OF_LANES $NUM_OF_SDIO ad_connect spi_clk data_capture/clk ad_connect ad463x_spi_cs data_capture/csn diff --git a/projects/ad4630_fmc/zed/README.md b/projects/ad4630_fmc/zed/README.md index 0406612123e..eece528f100 100644 --- a/projects/ad4630_fmc/zed/README.md +++ b/projects/ad4630_fmc/zed/README.md @@ -25,8 +25,8 @@ The overwritable parameters from the environment are: - CLK_MODE: clocking mode of the device's digital interface - 0 - SPI (default) - - 1 - Echo-clock or Master clock -- NUM_OF_SDI: the number of MISO lines of the SPI interface + - 1 - Echo-clock or Master clock +- NUM_OF_SDIO: the number of MOSI lines of the SPI interface - 1 - Interleaved - 2 - 1LPC - 4 - 2LPC (default) @@ -50,7 +50,7 @@ The overwritable parameters from the environment are: This specific command is equivalent to running `make` only: ``` -make CLK_MODE=0 NUM_OF_SDI=4 CAPTURE_ZONE=2 DDR_EN=0 NO_REORDER=0 +make CLK_MODE=0 NUM_OF_SDIO=4 CAPTURE_ZONE=2 DDR_EN=0 NO_REORDER=0 ``` Corresponding device trees: @@ -60,7 +60,7 @@ Corresponding device trees: #### Clock mode SPI, MISO lines 2, Capture zone 2, SDR ``` -make CLK_MODE=0 NUM_OF_SDI=2 CAPTURE_ZONE=2 DDR_EN=0 NO_REORDER=0 +make CLK_MODE=0 NUM_OF_SDIO=2 CAPTURE_ZONE=2 DDR_EN=0 NO_REORDER=0 ``` Corresponding device trees: @@ -80,43 +80,43 @@ make CLK_MODE=0 NUM_OF_SDI=4 CAPTURE_ZONE=2 DDR_EN=0 NO_REORDER=0 #### Clock mode SPI, MISO lines 8, Capture zone 2, SDR ``` -make CLK_MODE=0 NUM_OF_SDI=8 CAPTURE_ZONE=2 DDR_EN=0 NO_REORDER=0 +make CLK_MODE=0 NUM_OF_SDIO=8 CAPTURE_ZONE=2 DDR_EN=0 NO_REORDER=0 ``` #### Clock mode ECHO, MISO lines 2, Capture zone 2, SDR ``` -make CLK_MODE=1 NUM_OF_SDI=2 CAPTURE_ZONE=2 DDR_EN=0 NO_REORDER=0 +make CLK_MODE=1 NUM_OF_SDIO=2 CAPTURE_ZONE=2 DDR_EN=0 NO_REORDER=0 ``` #### Clock mode ECHO, MISO lines 4, Capture zone 2, SDR ``` -make CLK_MODE=1 NUM_OF_SDI=4 CAPTURE_ZONE=2 DDR_EN=0 NO_REORDER=0 +make CLK_MODE=1 NUM_OF_SDIO=4 CAPTURE_ZONE=2 DDR_EN=0 NO_REORDER=0 ``` #### Clock mode ECHO, MISO lines 8, Capture zone 2, SDR ``` -make CLK_MODE=1 NUM_OF_SDI=8 CAPTURE_ZONE=2 DDR_EN=0 NO_REORDER=0 +make CLK_MODE=1 NUM_OF_SDIO=8 CAPTURE_ZONE=2 DDR_EN=0 NO_REORDER=0 ``` #### Clock mode ECHO, MISO lines 2, Capture zone 2, DDR ``` -make CLK_MODE=1 NUM_OF_SDI=2 CAPTURE_ZONE=2 DDR_EN=1 NO_REORDER=0 +make CLK_MODE=1 NUM_OF_SDIO=2 CAPTURE_ZONE=2 DDR_EN=1 NO_REORDER=0 ``` #### Clock mode ECHO, MISO lines 4, Capture zone 2, DDR ``` -make CLK_MODE=1 NUM_OF_SDI=4 CAPTURE_ZONE=2 DDR_EN=1 NO_REORDER=0 +make CLK_MODE=1 NUM_OF_SDIO=4 CAPTURE_ZONE=2 DDR_EN=1 NO_REORDER=0 ``` #### Clock mode ECHO, MISO lines 8, Capture zone 2, DDR ``` -make CLK_MODE=1 NUM_OF_SDI=8 CAPTURE_ZONE=2 DDR_EN=1 NO_REORDER=0 +make CLK_MODE=1 NUM_OF_SDIO=8 CAPTURE_ZONE=2 DDR_EN=1 NO_REORDER=0 ``` #### Clock mode SPI, MISO lines 1, Capture zone 1, SDR (AD4030) diff --git a/projects/ad4630_fmc/zed/system_bd.tcl b/projects/ad4630_fmc/zed/system_bd.tcl index a2bfc589676..65d34c61b5a 100644 --- a/projects/ad4630_fmc/zed/system_bd.tcl +++ b/projects/ad4630_fmc/zed/system_bd.tcl @@ -20,7 +20,7 @@ ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "$mem_init_sys_file_path/mem_init_ ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 set sys_cstring "CLK_MODE=$ad_project_params(CLK_MODE)\ -NUM_OF_SDI=$ad_project_params(NUM_OF_SDI)\ +NUM_OF_SDIO=$ad_project_params(NUM_OF_SDIO)\ CAPTURE_ZONE=$ad_project_params(CAPTURE_ZONE)\ DDR_EN=$ad_project_params(DDR_EN)\ NO_REORDER=$ad_project_params(NO_REORDER)" diff --git a/projects/ad4630_fmc/zed/system_project.tcl b/projects/ad4630_fmc/zed/system_project.tcl index 45d56750e6c..a4536d60a79 100644 --- a/projects/ad4630_fmc/zed/system_project.tcl +++ b/projects/ad4630_fmc/zed/system_project.tcl @@ -13,7 +13,7 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl # How to use over-writable parameters from the environment: # # e.g. -# make NUM_OF_SDI=4 CAPTURE_ZONE=2 +# make NUM_OF_SDIO=4 CAPTURE_ZONE=2 # # # Parameter description: @@ -23,7 +23,7 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl # 0 - SPI Mode # 1 - Echo-clock or Master clock mode # -# NUM_OF_SDI : the number of MOSI lines of the SPI interface +# NUM_OF_SDIO : the number of MOSI lines of the SPI interface # # 1 - Interleaved mode # 2 - 1 lane per channel @@ -52,12 +52,12 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl # # Example: # -# make NUM_OF_SDI=2 CAPTURE_ZONE=2 +# make NUM_OF_SDIO=2 CAPTURE_ZONE=2 # adi_project ad4630_fmc_zed 0 [list \ CLK_MODE [get_env_param CLK_MODE 0] \ - NUM_OF_SDI [get_env_param NUM_OF_SDI 4] \ + NUM_OF_SDIO [get_env_param NUM_OF_SDIO 4] \ CAPTURE_ZONE [get_env_param CAPTURE_ZONE 2] \ DDR_EN [get_env_param DDR_EN 0] \ NO_REORDER [get_env_param NO_REORDER 0] ] @@ -69,7 +69,7 @@ adi_project_files ad4630_fmc_zed [list \ "system_constr.xdc" \ "system_top.v" ] -switch [get_env_param NUM_OF_SDI 4] { +switch [get_env_param NUM_OF_SDIO 4] { 1 { adi_project_files ad4630_fmc_zed [list \ "system_constr_1sdi.xdc" ] diff --git a/projects/ad4630_fmc/zed/system_top.v b/projects/ad4630_fmc/zed/system_top.v index cf55b9eea60..f873aca8d43 100644 --- a/projects/ad4630_fmc/zed/system_top.v +++ b/projects/ad4630_fmc/zed/system_top.v @@ -36,7 +36,7 @@ `timescale 1ns/100ps module system_top #( - parameter NUM_OF_SDI = 2 + parameter NUM_OF_SDIO = 2 ) ( inout [14:0] ddr_addr, inout [ 2:0] ddr_ba, @@ -86,7 +86,7 @@ module system_top #( // ad463x SPI configuration interface - input [NUM_OF_SDI-1:0] ad463x_spi_sdi, + input [NUM_OF_SDIO-1:0] ad463x_spi_sdi, output ad463x_spi_sdo, output ad463x_spi_sclk, output ad463x_spi_cs, diff --git a/projects/ad469x_evb/common/ad469x_qsys.tcl b/projects/ad469x_evb/common/ad469x_qsys.tcl index 9f65c2bf607..62fce4c6b70 100644 --- a/projects/ad469x_evb/common/ad469x_qsys.tcl +++ b/projects/ad469x_evb/common/ad469x_qsys.tcl @@ -19,21 +19,21 @@ add_instance axi_spi_engine_0 axi_spi_engine set_instance_parameter_value axi_spi_engine_0 {ASYNC_SPI_CLK} {1} set_instance_parameter_value axi_spi_engine_0 {DATA_WIDTH} {32} set_instance_parameter_value axi_spi_engine_0 {MM_IF_TYPE} {0} -set_instance_parameter_value axi_spi_engine_0 {NUM_OF_SDI} {1} +set_instance_parameter_value axi_spi_engine_0 {NUM_OF_SDIO} {1} set_instance_parameter_value axi_spi_engine_0 {NUM_OFFLOAD} {1} # spi_engine_execution add_instance spi_engine_execution_0 spi_engine_execution set_instance_parameter_value spi_engine_execution_0 {DATA_WIDTH} {32} -set_instance_parameter_value spi_engine_execution_0 {NUM_OF_SDI} {1} +set_instance_parameter_value spi_engine_execution_0 {NUM_OF_SDIO} {1} set_instance_parameter_value spi_engine_execution_0 {SDI_DELAY} {0} # spi_engine_interconnect add_instance spi_engine_interconnect_0 spi_engine_interconnect set_instance_parameter_value spi_engine_interconnect_0 {DATA_WIDTH} {32} -set_instance_parameter_value spi_engine_interconnect_0 {NUM_OF_SDI} {1} +set_instance_parameter_value spi_engine_interconnect_0 {NUM_OF_SDIO} {1} # bridges @@ -53,7 +53,7 @@ add_instance spi_engine_offload_0 spi_engine_offload set_instance_parameter_value spi_engine_offload_0 {ASYNC_TRIG} {1} set_instance_parameter_value spi_engine_offload_0 {ASYNC_SPI_CLK} {0} set_instance_parameter_value spi_engine_offload_0 {DATA_WIDTH} {32} -set_instance_parameter_value spi_engine_offload_0 {NUM_OF_SDI} {1} +set_instance_parameter_value spi_engine_offload_0 {NUM_OF_SDIO} {1} # axi pwm gen diff --git a/projects/ad5766_sdz/common/ad5766_bd.tcl b/projects/ad5766_sdz/common/ad5766_bd.tcl index 91ca3bd67a0..a4f4e3cbf0b 100644 --- a/projects/ad5766_sdz/common/ad5766_bd.tcl +++ b/projects/ad5766_sdz/common/ad5766_bd.tcl @@ -26,7 +26,7 @@ current_bd_instance /spi ad_ip_parameter execution CONFIG.NUM_OF_CS 1 ad_ip_parameter axi CONFIG.NUM_OFFLOAD 1 - ad_ip_parameter interconnect CONFIG.NUM_OF_SDI 2 + ad_ip_parameter interconnect CONFIG.NUM_OF_SDIO 2 ad_connect axi/spi_engine_offload_ctrl0 axi_ad5766/spi_engine_offload_ctrl ad_connect axi/spi_engine_ctrl interconnect/s0_ctrl diff --git a/projects/ad57xx_ardz/common/ad57xx_ardz_qsys.tcl b/projects/ad57xx_ardz/common/ad57xx_ardz_qsys.tcl index e19c5a53202..0ab0f351341 100644 --- a/projects/ad57xx_ardz/common/ad57xx_ardz_qsys.tcl +++ b/projects/ad57xx_ardz/common/ad57xx_ardz_qsys.tcl @@ -18,21 +18,21 @@ add_instance axi_spi_engine_0 axi_spi_engine set_instance_parameter_value axi_spi_engine_0 {ASYNC_SPI_CLK} {1} set_instance_parameter_value axi_spi_engine_0 {DATA_WIDTH} {32} set_instance_parameter_value axi_spi_engine_0 {MM_IF_TYPE} {0} -set_instance_parameter_value axi_spi_engine_0 {NUM_OF_SDI} {1} +set_instance_parameter_value axi_spi_engine_0 {NUM_OF_SDIO} {1} set_instance_parameter_value axi_spi_engine_0 {NUM_OFFLOAD} {1} # spi_engine_execution add_instance spi_engine_execution_0 spi_engine_execution set_instance_parameter_value spi_engine_execution_0 {DATA_WIDTH} {32} -set_instance_parameter_value spi_engine_execution_0 {NUM_OF_SDI} {1} +set_instance_parameter_value spi_engine_execution_0 {NUM_OF_SDIO} {1} set_instance_parameter_value spi_engine_execution_0 {SDI_DELAY} {0} # spi_engine_interconnect add_instance spi_engine_interconnect_0 spi_engine_interconnect set_instance_parameter_value spi_engine_interconnect_0 {DATA_WIDTH} {32} -set_instance_parameter_value spi_engine_interconnect_0 {NUM_OF_SDI} {1} +set_instance_parameter_value spi_engine_interconnect_0 {NUM_OF_SDIO} {1} # spi_engine_offload @@ -40,7 +40,7 @@ add_instance spi_engine_offload_0 spi_engine_offload set_instance_parameter_value spi_engine_offload_0 {ASYNC_TRIG} {1} set_instance_parameter_value spi_engine_offload_0 {ASYNC_SPI_CLK} {0} set_instance_parameter_value spi_engine_offload_0 {DATA_WIDTH} {32} -set_instance_parameter_value spi_engine_offload_0 {NUM_OF_SDI} {1} +set_instance_parameter_value spi_engine_offload_0 {NUM_OF_SDIO} {1} set_instance_parameter_value spi_engine_offload_0 {SDO_STREAMING} {1} # axi pwm gen diff --git a/projects/ad738x_fmc/common/ad738x_bd.tcl b/projects/ad738x_fmc/common/ad738x_bd.tcl index 6bdd0d53045..24353c4e33b 100644 --- a/projects/ad738x_fmc/common/ad738x_bd.tcl +++ b/projects/ad738x_fmc/common/ad738x_bd.tcl @@ -6,10 +6,10 @@ # system level parameter set ALERT_SPI_N $ad_project_params(ALERT_SPI_N) -set NUM_OF_SDI $ad_project_params(NUM_OF_SDI) +set NUM_OF_SDIO $ad_project_params(NUM_OF_SDIO) puts "build parameter: ALERT_SPI_N: $ALERT_SPI_N" -puts "build parameter: NUM_OF_SDI: $NUM_OF_SDI" +puts "build parameter: NUM_OF_SDIO: $NUM_OF_SDIO" create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_engine_rtl:1.0 ad738x_spi @@ -18,7 +18,7 @@ source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl set data_width 32 set async_spi_clk 1 set num_cs 1 -set num_sdi [expr {$ALERT_SPI_N ? 1 : $NUM_OF_SDI}] +set num_sdi [expr {$ALERT_SPI_N ? 1 : $NUM_OF_SDIO}] set num_sdo 1 set sdi_delay 1 set echo_sclk 0 diff --git a/projects/ad738x_fmc/zed/README.md b/projects/ad738x_fmc/zed/README.md index e2479a4fe61..bebab3466ef 100644 --- a/projects/ad738x_fmc/zed/README.md +++ b/projects/ad738x_fmc/zed/README.md @@ -15,10 +15,10 @@ The overwritable parameters from the environment: - 0 - SDOB-SDOD - 1 - ALERT -- NUM_OF_SDI - Defines the number of SDI lines used: 1, 2, 4 +- NUM_OF_SDIO - Defines the number of SDI lines used: 1, 2, 4 For the ALERT functionality, the following parameter will be used in `make` command: ALERT_SPI_N. -For the serial data output functionality, the following parameters will be used in `make` command: ALERT_SPI_N, NUM_OF_SDI. +For the serial data output functionality, the following parameters will be used in `make` command: ALERT_SPI_N, NUM_OF_SDIO. ### Example configurations @@ -28,7 +28,7 @@ This specific command is equivalent to running `make` only: ``` cd projects/ad738x_fmc/zed -make ALERT_SPI_N=0 NUM_OF_SDI=1 +make ALERT_SPI_N=0 NUM_OF_SDIO=1 ``` Corresponding device tree: [zynq-zed-adv7511-ad7380.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad7380.dts) \ No newline at end of file diff --git a/projects/ad738x_fmc/zed/system_project.tcl b/projects/ad738x_fmc/zed/system_project.tcl index b961dd11e91..eab141d56ac 100644 --- a/projects/ad738x_fmc/zed/system_project.tcl +++ b/projects/ad738x_fmc/zed/system_project.tcl @@ -11,12 +11,12 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl # ALERT_SPI_N - SDOB-SDOD/ALERT pin can operate as a serial data output pin or alert indication output # - Options : SDOB-SDOD(0)/ALERT(1) -# NUM_OF_SDI - Number of SDI lines used +# NUM_OF_SDIO - Number of SDI lines used # - Options : 1,2,4 adi_project ad738x_fmc_zed 0 [list \ ALERT_SPI_N [get_env_param ALERT_SPI_N 0]\ - NUM_OF_SDI [get_env_param NUM_OF_SDI 1] ] + NUM_OF_SDIO [get_env_param NUM_OF_SDIO 1] ] adi_project_files ad738x_fmc_zed [list \ "$ad_hdl_dir/library/common/ad_iobuf.v" \ @@ -24,7 +24,7 @@ adi_project_files ad738x_fmc_zed [list \ "system_constr.xdc" \ "system_top.v" ] -switch [get_env_param NUM_OF_SDI 1] { +switch [get_env_param NUM_OF_SDIO 1] { 1 { adi_project_files ad738x_fmc_zed [list \ "system_constr_1sdi.xdc" ] diff --git a/projects/ad738x_fmc/zed/system_top.v b/projects/ad738x_fmc/zed/system_top.v index 6cc61a3f188..a361d989f01 100644 --- a/projects/ad738x_fmc/zed/system_top.v +++ b/projects/ad738x_fmc/zed/system_top.v @@ -37,7 +37,7 @@ module system_top #( parameter ALERT_SPI_N = 0, - parameter NUM_OF_SDI = 1 + parameter NUM_OF_SDIO = 1 ) ( inout [14:0] ddr_addr, inout [ 2:0] ddr_ba, @@ -106,7 +106,7 @@ module system_top #( wire [ 1:0] iic_mux_sda_o_s; wire iic_mux_sda_t_s; - wire [NUM_OF_SDI-1:0] ad738x_spi_sdi_s; + wire [NUM_OF_SDIO-1:0] ad738x_spi_sdi_s; // instantiations @@ -115,7 +115,7 @@ module system_top #( assign gpio_i[32] = ALERT_SPI_N ? spi_sdib : 0; assign gpio_i[33] = ALERT_SPI_N ? spi_sdid : 0; - assign ad738x_spi_sdi_s = (ALERT_SPI_N == 0) ? ((NUM_OF_SDI == 1) ? {spi_sdia} : ((NUM_OF_SDI == 4) ? {spi_sdid, spi_sdic, spi_sdib, spi_sdia} : {spi_sdib, spi_sdia})): spi_sdia; + assign ad738x_spi_sdi_s = (ALERT_SPI_N == 0) ? ((NUM_OF_SDIO == 1) ? {spi_sdia} : ((NUM_OF_SDIO == 4) ? {spi_sdid, spi_sdic, spi_sdib, spi_sdia} : {spi_sdib, spi_sdia})): spi_sdia; ad_iobuf #( .DATA_WIDTH(32) diff --git a/projects/ad7606x_fmc/common/ad7606x_bd.tcl b/projects/ad7606x_fmc/common/ad7606x_bd.tcl index 2ea60699faf..289cf89ec60 100644 --- a/projects/ad7606x_fmc/common/ad7606x_bd.tcl +++ b/projects/ad7606x_fmc/common/ad7606x_bd.tcl @@ -5,13 +5,13 @@ # system level parameters set INTF $ad_project_params(INTF) -set NUM_OF_SDI $ad_project_params(NUM_OF_SDI) +set NUM_OF_SDIO $ad_project_params(NUM_OF_SDIO) set ADC_N_BITS $ad_project_params(ADC_N_BITS) set ADC_TO_DMA_N_BITS [expr {$ADC_N_BITS == 16 ? 16 : 32}] set TOTAL_N_BITS_DMA [expr {$ADC_TO_DMA_N_BITS*8}] puts "build parameters: INTF: $INTF" -puts "build parameters: NUM_OF_SDI: $NUM_OF_SDI" +puts "build parameters: NUM_OF_SDIO: $NUM_OF_SDIO" puts "build parameters: ADC_N_BITS: $ADC_N_BITS" # control lines @@ -119,7 +119,7 @@ switch $INTF { set data_width 32 set async_spi_clk 1 set num_cs 1 - set num_sdi $NUM_OF_SDI + set num_sdi $NUM_OF_SDIO set num_sdo 1 set sdi_delay 1 diff --git a/projects/ad7606x_fmc/zed/README.md b/projects/ad7606x_fmc/zed/README.md index 36db4e5cf60..bce9747dac2 100644 --- a/projects/ad7606x_fmc/zed/README.md +++ b/projects/ad7606x_fmc/zed/README.md @@ -14,12 +14,12 @@ All of the configuration modes can be found in the chosen chips's data sheet. We - INTF - Defines the operation interface - 0 - Parallel - 1 - Serial -- NUM_OF_SDI - Defines the number of SDI lines used: 1, 2, 4 or 8 +- NUM_OF_SDIO - Defines the number of SDI lines used: 1, 2, 4 or 8 - ADC_N_BITS - Specifies the ADC resolution: 16 or 18 bits (only for the Parallel Interface) For the serial interface (INTF=1), the following parameters will be used in make command: - INTF -- NUM_OF_SDI. +- NUM_OF_SDIO. For the parallel interface (INTF=0), the following parameters will be used in make command: - INTF @@ -47,25 +47,25 @@ make INTF=0 ADC_N_BITS=18 #### Serial interface with 1 SDI line ``` -make INTF=1 NUM_OF_SDI=1 +make INTF=1 NUM_OF_SDIO=1 ``` #### Serial interface with 2 SDI lines ``` -make INTF=1 NUM_OF_SDI=2 +make INTF=1 NUM_OF_SDIO=2 ``` #### Serial interface with 4 SDI lines ``` -make INTF=1 NUM_OF_SDI=4 +make INTF=1 NUM_OF_SDIO=4 ``` #### Serial interface with 8 SDI lines ``` -make INTF=1 NUM_OF_SDI=8 +make INTF=1 NUM_OF_SDIO=8 ``` Corresponding no-OS project: [ad7606x-fmc](https://github.com/analogdevicesinc/no-OS/tree/main/projects/ad7606x-fmc) diff --git a/projects/ad7606x_fmc/zed/system_bd.tcl b/projects/ad7606x_fmc/zed/system_bd.tcl index 3a308dcf580..461d05dddcc 100644 --- a/projects/ad7606x_fmc/zed/system_bd.tcl +++ b/projects/ad7606x_fmc/zed/system_bd.tcl @@ -21,6 +21,6 @@ ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 set sys_cstring "INTF=$ad_project_params(INTF)\ ADC_N_BITS=$ad_project_params(ADC_N_BITS)\ -NUM_OF_SDI=$ad_project_params(NUM_OF_SDI)" +NUM_OF_SDIO=$ad_project_params(NUM_OF_SDIO)" sysid_gen_sys_init_file $sys_cstring diff --git a/projects/ad7606x_fmc/zed/system_project.tcl b/projects/ad7606x_fmc/zed/system_project.tcl index 15630913a14..3f6970c2fed 100644 --- a/projects/ad7606x_fmc/zed/system_project.tcl +++ b/projects/ad7606x_fmc/zed/system_project.tcl @@ -10,18 +10,18 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl # Parameter description # INTF - Operation interface # - Options : Parallel(0)/Serial(1) -# NUM_OF_SDI - Number of SDI lines used +# NUM_OF_SDIO - Number of SDI lines used # - Options: 1, 2, 4, 8 # ADC_N_BITS - ADC resolution # - Options: 16, 18 -set NUM_OF_SDI [get_env_param NUM_OF_SDI 2] +set NUM_OF_SDIO [get_env_param NUM_OF_SDIO 2] set ADC_N_BITS [get_env_param ADC_N_BITS 16] set INTF [get_env_param INTF 0] adi_project ad7606x_fmc_zed 0 [list \ INTF $INTF \ - NUM_OF_SDI $NUM_OF_SDI \ + NUM_OF_SDIO $NUM_OF_SDIO \ ADC_N_BITS $ADC_N_BITS \ ] @@ -36,7 +36,7 @@ switch $INTF { "system_constr_pif.xdc"] } 1 { - switch $NUM_OF_SDI { + switch $NUM_OF_SDIO { 1 { adi_project_files ad7606x_fmc_zed [list \ "system_top_si.v" \ diff --git a/projects/ad7606x_fmc/zed/system_top_si.v b/projects/ad7606x_fmc/zed/system_top_si.v index 8d0244832ec..b906c9e9d15 100644 --- a/projects/ad7606x_fmc/zed/system_top_si.v +++ b/projects/ad7606x_fmc/zed/system_top_si.v @@ -36,7 +36,7 @@ `timescale 1ns/100ps module system_top #( - parameter NUM_OF_SDI = 2 + parameter NUM_OF_SDIO = 2 ) ( inout [14:0] ddr_addr, inout [ 2:0] ddr_ba, @@ -86,7 +86,7 @@ module system_top #( output ad7606_spi_cs, output ad7606_spi_sclk, - input [NUM_OF_SDI-1:0] ad7606_spi_sdi, + input [NUM_OF_SDIO-1:0] ad7606_spi_sdi, output ad7606_spi_sdo, inout adc_serpar, diff --git a/projects/ad7616_sdz/common/ad7616_bd.tcl b/projects/ad7616_sdz/common/ad7616_bd.tcl index d628377c6ef..86dfb47a486 100644 --- a/projects/ad7616_sdz/common/ad7616_bd.tcl +++ b/projects/ad7616_sdz/common/ad7616_bd.tcl @@ -7,10 +7,10 @@ # system level parameter set INTF $ad_project_params(INTF) -set NUM_OF_SDI $ad_project_params(NUM_OF_SDI) +set NUM_OF_SDIO $ad_project_params(NUM_OF_SDIO) puts "build parameters: INTF: $INTF" -puts "build parameters: NUM_OF_SDI: $NUM_OF_SDI" +puts "build parameters: NUM_OF_SDIO: $NUM_OF_SDIO" # control lines @@ -54,7 +54,7 @@ if {$INTF == 1} { set data_width 16 set async_spi_clk 1 set num_cs 1 - set num_sdi $NUM_OF_SDI + set num_sdi $NUM_OF_SDIO set sdi_delay 1 set hier_spi_engine spi_ad7616 diff --git a/projects/ad7616_sdz/zed/README.md b/projects/ad7616_sdz/zed/README.md index f558ed30e29..626415d07fa 100644 --- a/projects/ad7616_sdz/zed/README.md +++ b/projects/ad7616_sdz/zed/README.md @@ -19,7 +19,7 @@ The overwritable parameter from the environment: - 0 - parallel interface (default) - 1 - serial interface -- NUM_OF_SDI - specifies the number of SDI lines used when **serial interface** is set; +- NUM_OF_SDIO - specifies the number of SDI lines used when **serial interface** is set; - 1 - one SDI line - 2 - two SDI lines (default) @@ -41,10 +41,10 @@ make INTF=0 #### Serial interface ``` -make INTF=1 NUM_OF_SDI=1 +make INTF=1 NUM_OF_SDIO=1 ``` ``` -make INTF=1 NUM_OF_SDI=2 +make INTF=1 NUM_OF_SDIO=2 ``` Corresponding No-OS project for both configurations: [ad7616-sdz](https://github.com/analogdevicesinc/no-OS/tree/main/projects/ad7616-sdz) diff --git a/projects/ad7616_sdz/zed/system_bd.tcl b/projects/ad7616_sdz/zed/system_bd.tcl index c01e8ba4791..8f5b38caf82 100644 --- a/projects/ad7616_sdz/zed/system_bd.tcl +++ b/projects/ad7616_sdz/zed/system_bd.tcl @@ -20,6 +20,6 @@ ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "$mem_init_sys_file_path/mem_init_ ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 set sys_cstring "INTF=$ad_project_params(INTF)\ -NUM_OF_SDI=$ad_project_params(NUM_OF_SDI)" +NUM_OF_SDIO=$ad_project_params(NUM_OF_SDIO)" sysid_gen_sys_init_file $sys_cstring diff --git a/projects/ad7616_sdz/zed/system_project.tcl b/projects/ad7616_sdz/zed/system_project.tcl index c252a4181fd..c478cc1bb24 100644 --- a/projects/ad7616_sdz/zed/system_project.tcl +++ b/projects/ad7616_sdz/zed/system_project.tcl @@ -21,7 +21,7 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl # INTF - Defines the interface type (serial OR parallel) # - 0 - parallel (default) # - 1 - serial -# NUM_OF_SDI - Number of SDI lines used when **serial interface** is set +# NUM_OF_SDIO - Number of SDI lines used when **serial interface** is set # - 1 - one SDI line # - 2 - two SDI lines (default) # @@ -33,11 +33,11 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl ##-------------------------------------------------------------- set INTF [get_env_param INTF 0] -set NUM_OF_SDI [get_env_param NUM_OF_SDI 2] +set NUM_OF_SDIO [get_env_param NUM_OF_SDIO 2] adi_project ad7616_sdz_zed 0 [list \ INTF $INTF \ - NUM_OF_SDI $NUM_OF_SDI \ + NUM_OF_SDIO $NUM_OF_SDIO \ ] adi_project_files ad7616_sdz_zed [list \ @@ -45,7 +45,7 @@ adi_project_files ad7616_sdz_zed [list \ switch $INTF { 1 { - switch $NUM_OF_SDI { + switch $NUM_OF_SDIO { 1 { adi_project_files ad7616_sdz_zed [list \ "system_top_si.v" \ diff --git a/projects/ad7616_sdz/zed/system_top_si.v b/projects/ad7616_sdz/zed/system_top_si.v index df44946ea78..230e8385d58 100644 --- a/projects/ad7616_sdz/zed/system_top_si.v +++ b/projects/ad7616_sdz/zed/system_top_si.v @@ -36,7 +36,7 @@ `timescale 1ns/100ps module system_top #( - parameter NUM_OF_SDI = 2 + parameter NUM_OF_SDIO = 2 ) ( inout [14:0] ddr_addr, inout [ 2:0] ddr_ba, @@ -78,7 +78,7 @@ module system_top #( input otg_vbusoc, output ad7616_spi_sclk, output ad7616_spi_sdo, - input [NUM_OF_SDI-1:0] ad7616_spi_sdi, + input [NUM_OF_SDIO-1:0] ad7616_spi_sdi, output ad7616_spi_cs, output adc_reset_n, output adc_cnvst, diff --git a/projects/cn0540/common/cn0540_qsys.tcl b/projects/cn0540/common/cn0540_qsys.tcl index b1864195538..0edb9c5803b 100755 --- a/projects/cn0540/common/cn0540_qsys.tcl +++ b/projects/cn0540/common/cn0540_qsys.tcl @@ -18,21 +18,21 @@ add_instance axi_spi_engine_0 axi_spi_engine set_instance_parameter_value axi_spi_engine_0 {ASYNC_SPI_CLK} {1} set_instance_parameter_value axi_spi_engine_0 {DATA_WIDTH} {32} set_instance_parameter_value axi_spi_engine_0 {MM_IF_TYPE} {0} -set_instance_parameter_value axi_spi_engine_0 {NUM_OF_SDI} {1} +set_instance_parameter_value axi_spi_engine_0 {NUM_OF_SDIO} {1} set_instance_parameter_value axi_spi_engine_0 {NUM_OFFLOAD} {1} # spi_engine_execution add_instance spi_engine_execution_0 spi_engine_execution set_instance_parameter_value spi_engine_execution_0 {DATA_WIDTH} {32} -set_instance_parameter_value spi_engine_execution_0 {NUM_OF_SDI} {1} +set_instance_parameter_value spi_engine_execution_0 {NUM_OF_SDIO} {1} set_instance_parameter_value spi_engine_execution_0 {SDI_DELAY} {0} # spi_engine_interconnect add_instance spi_engine_interconnect_0 spi_engine_interconnect set_instance_parameter_value spi_engine_interconnect_0 {DATA_WIDTH} {32} -set_instance_parameter_value spi_engine_interconnect_0 {NUM_OF_SDI} {1} +set_instance_parameter_value spi_engine_interconnect_0 {NUM_OF_SDIO} {1} # spi_engine_offload @@ -40,7 +40,7 @@ add_instance spi_engine_offload_0 spi_engine_offload set_instance_parameter_value spi_engine_offload_0 {ASYNC_TRIG} {1} set_instance_parameter_value spi_engine_offload_0 {ASYNC_SPI_CLK} {0} set_instance_parameter_value spi_engine_offload_0 {DATA_WIDTH} {32} -set_instance_parameter_value spi_engine_offload_0 {NUM_OF_SDI} {1} +set_instance_parameter_value spi_engine_offload_0 {NUM_OF_SDIO} {1} # exported interface diff --git a/projects/cn0561/common/cn0561_qsys.tcl b/projects/cn0561/common/cn0561_qsys.tcl index d9776bf7872..a748e4114f9 100644 --- a/projects/cn0561/common/cn0561_qsys.tcl +++ b/projects/cn0561/common/cn0561_qsys.tcl @@ -17,21 +17,21 @@ add_instance axi_spi_engine_0 axi_spi_engine set_instance_parameter_value axi_spi_engine_0 {ASYNC_SPI_CLK} {1} set_instance_parameter_value axi_spi_engine_0 {DATA_WIDTH} {32} set_instance_parameter_value axi_spi_engine_0 {MM_IF_TYPE} {0} -set_instance_parameter_value axi_spi_engine_0 {NUM_OF_SDI} {4} +set_instance_parameter_value axi_spi_engine_0 {NUM_OF_SDIO} {4} set_instance_parameter_value axi_spi_engine_0 {NUM_OFFLOAD} {1} # spi_engine_execution add_instance spi_engine_execution_0 spi_engine_execution set_instance_parameter_value spi_engine_execution_0 {DATA_WIDTH} {32} -set_instance_parameter_value spi_engine_execution_0 {NUM_OF_SDI} {4} +set_instance_parameter_value spi_engine_execution_0 {NUM_OF_SDIO} {4} set_instance_parameter_value spi_engine_execution_0 {SDI_DELAY} {0} # spi_engine_interconnect add_instance spi_engine_interconnect_0 spi_engine_interconnect set_instance_parameter_value spi_engine_interconnect_0 {DATA_WIDTH} {32} -set_instance_parameter_value spi_engine_interconnect_0 {NUM_OF_SDI} {4} +set_instance_parameter_value spi_engine_interconnect_0 {NUM_OF_SDIO} {4} # spi_engine_offload @@ -39,7 +39,7 @@ add_instance spi_engine_offload_0 spi_engine_offload set_instance_parameter_value spi_engine_offload_0 {ASYNC_TRIG} {1} set_instance_parameter_value spi_engine_offload_0 {ASYNC_SPI_CLK} {0} set_instance_parameter_value spi_engine_offload_0 {DATA_WIDTH} {32} -set_instance_parameter_value spi_engine_offload_0 {NUM_OF_SDI} {4} +set_instance_parameter_value spi_engine_offload_0 {NUM_OF_SDIO} {4} # axi pwm gen diff --git a/projects/script_to_find_spi_engine_projects.sh b/projects/script_to_find_spi_engine_projects.sh new file mode 100755 index 00000000000..600f7af7b63 --- /dev/null +++ b/projects/script_to_find_spi_engine_projects.sh @@ -0,0 +1,19 @@ +#!/bin/bash + +while IFS= read -rd ''; do + targets+=("$REPLY") +done < <(grep -iRlw --null "spi_engine_create" .) + +# check content of array +declare -p targets + +for file in "${targets[@]}"; do + folders+=$(dirname "$file" | cut -d/ -f2) +done + +echo $folders[0] +echo $folders[1] + +for index in "${!folders[@]}"; do + echo "$index ${fds[index]}" +done