diff --git a/library/data_offload/data_offload.v b/library/data_offload/data_offload.v
index 5fc30db3046..7078b77e9c6 100644
--- a/library/data_offload/data_offload.v
+++ b/library/data_offload/data_offload.v
@@ -228,16 +228,6 @@ module data_offload #(
     .wr_fsm_state_out (src_fsm_status_s),
     .rd_fsm_state_out (dst_fsm_status_s));
 
-  assign m_axis_valid = dst_bypass_s ? valid_bypass_s : (rd_ready & s_storage_axis_valid);
-  // For DAC paths set zero as IDLE data on the axis bus, avoid repeating last
-  // sample.
-  assign m_axis_data  = TX_OR_RXN_PATH[0] & ~m_axis_valid ? {DST_DATA_WIDTH{1'b0}} :
-                        (dst_bypass_s) ? data_bypass_s  : s_storage_axis_data;
-  assign m_axis_last  = (dst_bypass_s) ? 1'b0           : s_storage_axis_last;
-  assign m_axis_tkeep = (dst_bypass_s) ? {DST_DATA_WIDTH/8{1'b1}} : s_storage_axis_tkeep;
-
-  assign s_axis_ready =  src_bypass_s ? ready_bypass_s : (wr_ready & m_storage_axis_ready);
-
   assign m_storage_axis_valid = s_axis_valid & wr_ready;
   assign m_storage_axis_data = s_axis_data;
   assign m_storage_axis_last = s_axis_last;
@@ -248,32 +238,58 @@ module data_offload #(
   // Bypass module instance -- the same FIFO, just a smaller depth
   // NOTE: Generating an overflow is making sense just in BYPASS mode, and
   // it's supported just with the FIFO interface
-  util_axis_fifo_asym #(
-    .S_DATA_WIDTH (SRC_DATA_WIDTH),
-    .ADDRESS_WIDTH (SRC_ADDR_WIDTH_BYPASS),
-    .M_DATA_WIDTH (DST_DATA_WIDTH),
-    .ASYNC_CLK (1)
-  ) i_bypass_fifo (
-    .m_axis_aclk (m_axis_aclk),
-    .m_axis_aresetn (dst_rstn),
-    .m_axis_ready (m_axis_ready),
-    .m_axis_valid (valid_bypass_s),
-    .m_axis_data  (data_bypass_s),
-    .m_axis_tlast (),
-    .m_axis_empty (),
-    .m_axis_almost_empty (),
-    .m_axis_tkeep (),
-    .m_axis_level (),
-    .s_axis_aclk  (s_axis_aclk),
-    .s_axis_aresetn (src_rstn),
-    .s_axis_ready (ready_bypass_s),
-    .s_axis_valid (s_axis_valid & src_bypass_s),
-    .s_axis_data  (s_axis_data),
-    .s_axis_tlast (),
-    .s_axis_full  (),
-    .s_axis_almost_full (),
-    .s_axis_tkeep (),
-    .s_axis_room ());
+  generate if (HAS_BYPASS) begin
+    util_axis_fifo_asym #(
+      .S_DATA_WIDTH (SRC_DATA_WIDTH),
+      .ADDRESS_WIDTH (SRC_ADDR_WIDTH_BYPASS),
+      .M_DATA_WIDTH (DST_DATA_WIDTH),
+      .ASYNC_CLK (1)
+    ) i_bypass_fifo (
+      .m_axis_aclk (m_axis_aclk),
+      .m_axis_aresetn (dst_rstn),
+      .m_axis_ready (m_axis_ready),
+      .m_axis_valid (valid_bypass_s),
+      .m_axis_data  (data_bypass_s),
+      .m_axis_tlast (),
+      .m_axis_empty (),
+      .m_axis_almost_empty (),
+      .m_axis_tkeep (),
+      .m_axis_level (),
+      .s_axis_aclk  (s_axis_aclk),
+      .s_axis_aresetn (src_rstn),
+      .s_axis_ready (ready_bypass_s),
+      .s_axis_valid (s_axis_valid & src_bypass_s),
+      .s_axis_data  (s_axis_data),
+      .s_axis_tlast (),
+      .s_axis_full  (),
+      .s_axis_almost_full (),
+      .s_axis_tkeep (),
+      .s_axis_room ());
+
+      assign m_axis_valid = dst_bypass_s ? valid_bypass_s : (rd_ready & s_storage_axis_valid);
+      // For DAC paths set zero as IDLE data on the axis bus, avoid repeating last
+      // sample.
+      assign m_axis_data  = TX_OR_RXN_PATH[0] & ~m_axis_valid ? {DST_DATA_WIDTH{1'b0}} :
+                            (dst_bypass_s) ? data_bypass_s  : s_storage_axis_data;
+      assign m_axis_last  = (dst_bypass_s) ? 1'b0           : s_storage_axis_last;
+      assign m_axis_tkeep = (dst_bypass_s) ? {DST_DATA_WIDTH/8{1'b1}} : s_storage_axis_tkeep;
+      assign s_axis_ready =  src_bypass_s ? ready_bypass_s : (wr_ready & m_storage_axis_ready);
+  end else begin
+      assign valid_bypass_s = 1'b0;
+      assign data_bypass_s = 'd0;
+      assign ready_bypass_s = 1'b0;
+
+      assign m_axis_valid = (rd_ready & s_storage_axis_valid);
+      // For DAC paths set zero as IDLE data on the axis bus, avoid repeating last
+      // sample.
+      assign m_axis_data  = (TX_OR_RXN_PATH[0] & ~m_axis_valid) ? {DST_DATA_WIDTH{1'b0}} :
+                          s_storage_axis_data;
+      assign m_axis_last  = s_storage_axis_last;
+      assign m_axis_tkeep = s_storage_axis_tkeep;
+
+      assign s_axis_ready = (wr_ready & m_storage_axis_ready);
+  end
+  endgenerate
 
   // register map