Merge pull request #722 from aws/submodule-doc-links-fix

IP Submodule Link Updates

Author: AWSjoeluc

docs-rtd/source/hdk/README.rst

@@ -644,7 +644,7 @@ Verification
 
   - Simulation libraries can be found in
     `hdk/common/ip/cl_ip/cl_ip.ip_user_files/sim_scripts
-    <https://github.com/aws/aws-fpga/tree/f2/hdk/common/ip/cl_ip/cl_ip.ip_user_files/sim_scripts>`__
+    <https://github.com/aws/aws-fpga-resources/blob/-/cl_ip/cl_ip.ip_user_files/sim_scripts>`__
     followed by ``"IP_NAME"/"SIMULATOR"/"IP_NAME".sh``
 
 - Adding new IPs requires to recompile the simulation libraries
@@ -744,8 +744,8 @@ categorized under four subdirectories:
 ip/
 ~~~
 
-The `ip/ <https://github.com/aws/aws-fpga/tree/f2/hdk/common/ip>`__ directory
-includes all CL IPs .
+The `ip/ <https://github.com/aws/aws-fpga-resources>`__ directory
+includes all CL IPs.
 
 lib/
 ~~~~

docs-rtd/source/hdk/cl/examples/CL-TEMPLATE/README.rst

@@ -255,7 +255,7 @@ design files.
 
 Users may modify these files and add new ones as their designs grow.
 Xilinx IP's are available to all CL examples (found under
-`$AWS_FPGA_REPO_DIR/hdk/common/ip <https://github.com/aws/aws-fpga/tree/f2/hdk/common/ip>`__).
+`$AWS_FPGA_REPO_DIR/hdk/common/ip <https://github.com/aws/aws-fpga-resources/>`__).
 
 STEP 3: Develop Design Verification Tests (OPTIONAL)
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -285,7 +285,7 @@ This will first generate and compile the simulation libraries required for the
 requested SIMULATOR. Test results will be stored in the
 ``$CL_DIR/verif/sim/<SIMULATOR>`` directory (created upon first simulation
 run). After adding new IP's to
-`$AWS_FPGA_REPO_DIR/hdk/common/ip <https://github.com/aws/aws-fpga/tree/f2/hdk/common/ip>`__, the simulation
+`$AWS_FPGA_REPO_DIR/hdk/common/ip <https://github.com/aws/aws-fpga-resources/>`__, the simulation
 libraries need to be recompiled: ``make regenerate_sim_libs <SIMULATOR>=1``.
 
 File List Generation
@@ -318,7 +318,7 @@ Xilinx/AMD IP Discovery and Compilation
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
 When running your first test, all Xilinx IP's under
-`$AWS_FPGA_REPO_DIR/hdk/common/ip/cl_ip <https://github.com/aws/aws-fpga/tree/f2/hdk/common/ip/cl_ip>`__
+`$AWS_FPGA_REPO_DIR/hdk/common/ip/cl_ip <https://github.com/aws/aws-fpga-resources/blob/-/cl_ip>`__
 are automatically compiled
 
 - You can find the ``xil_defaultlib`` library for each simulator in
@@ -335,7 +335,7 @@ to ``COMMON_LIBLISTS`` in:
 Simulation library names can be found under:
 
 - `$AWS_FPGA_REPO_DIR/hdk/common/ip/cl_ip/cl_ip.ip_user_files/sim_scripts
-  <https://github.com/aws/aws-fpga/tree/f2/hdk/common/ip/cl_ip/cl_ip.ip_user_files/sim_scripts>`__ followed
+  <https://github.com/aws/aws-fpga-resources/blob/-/cl_ip/cl_ip.ip_user_files/sim_scripts>`__ followed
   by ``<IP_NAME>/<SIMULATOR>/<IP_NAME>.sh``
 
 All verification work is located under the `verif <https://github.com/aws/aws-fpga/tree/f2/hdk/common/verif>`__
@@ -376,7 +376,7 @@ and build scripts can be found in other examples such as
      - IP's used in AWS example designs can uncommented be in
        `synth_CL_TEMPLATE.tcl <https://github.com/aws/aws-fpga/tree/f2/hdk/cl/examples/CL_TEMPLATE/build/scripts/synth_CL_TEMPLATE.tcl>`__
        and found under
-       `$AWS_FPGA_REPO_DIR/hdk/common/ip/cl_ip <https://github.com/aws/aws-fpga/tree/f2/hdk/common/ip/cl_ip>`__
+       `$AWS_FPGA_REPO_DIR/hdk/common/ip/cl_ip <https://github.com/aws/aws-fpga-resources/blob/-/cl_ip>`__
      - If a design adds new IP's, make sure to add the new ``xci`` files
        to the build script
        `$CL_DIR/build/scripts/synth_CL_TEMPLATE.tcl <https://github.com/aws/aws-fpga/tree/f2/hdk/cl/examples/CL_TEMPLATE/build/scripts/synth_CL_TEMPLATE.tcl>`__

docs-rtd/source/hdk/docs/AWS-Shell-Interface-Specification.rst

@@ -771,7 +771,7 @@ to HBM:
     true
 
   **NOTE:** This step can be skipped if the customer uses the
-  ``CL_HBM`` IP from the `CL examples <https://github.com/aws/aws-fpga/tree/f2/hdk/common/ip/cl_ip/cl_ip.runs>`__.
+  ``CL_HBM`` IP from the `CL examples <https://github.com/aws/aws-fpga-resources/blob/-/cl_ip/cl_ip.gen/sources_1/ip>`__.
   This IP has the ``MON_APB`` interface enabled and is ready to be
   integrated to a customer design as-is.
 
@@ -938,7 +938,7 @@ Please see the `Shell Floorplan <./shell-floorplan.html>`__ for additional
 details on Shell-CL interface placements in SMALL_SHELL.
 
 For the interfaces that are in both the MID/BOTTOM the recommendation is
-to use flops for pipelining, but don’t constrain to an SLR. You can
+to use flops for pipelining, but don't constrain to an SLR. You can
 constrain logic to a particular SLR by creating PBLOCKs (one per SLR),
 and assigning logic to the PBLOCKs (refer to cl_dram_hbm_dma example
 `small_shell_cl_pnr_user.xdc <https://github.com/aws/aws-fpga/tree/f2/hdk/cl/examples/cl_dram_hbm_dma/build/constraints/small_shell_cl_pnr_user.xdc>`__).

docs-rtd/source/hdk/docs/Supported-DDR-Modes.rst

@@ -81,7 +81,7 @@ Required Build Script Modifications
 -----------------------------------
 
 AWS provides following DDR Core IPs as part of Vivado
-`cl_ip.xpr <https://github.com/aws/aws-fpga/tree/f2/hdk/common/ip/cl_ip/cl_ip.xpr>`__ project. Users are
+`cl_ip.xpr <https://github.com/aws/aws-fpga-resources/blob/-/cl_ip/cl_ip.xpr>`__ project. Users are
 required to enlist one of the following XCI files in the synthesis
 scripts, depending on the desired DDR configuration and macros defined:
 

docs-rtd/source/hdk/docs/Virtual-JTAG-XVC.rst

@@ -212,7 +212,7 @@ Embedded Debug Bridge in CL
 ---------------------------
 
 The `CL_Debug_Bridge
-<https://github.com/aws/aws-fpga/tree/f2/hdk/common/ip/cl_ip/cl_ip.srcs/sources_1/ip/cl_debug_bridge/cl_debug_bridge.xci>`__
+<https://github.com/aws/aws-fpga-resources/blob/-/cl_ip/cl_ip.srcs/sources_1/ip/cl_debug_bridge/cl_debug_bridge.xci>`__
 IP must be embedded in the CL design to enable the use of debug cores like ILA
 and VIO. According to the `AMD user guide
 <https://docs.amd.com/r/en-US/ug908-vivado-programming-debugging/Debug-Cores-Clocking-Guidelines>`__

hdk/README.md

@@ -439,7 +439,7 @@ After adding new design IPs, make sure to add the new simulation `COMMON_LIBLIST
 
 - Make sure to add the new simulation libraries to `COMMON_LIBLISTS` in [$AWS_FPGA_REPO_DIR/hdk/common/verif/tb/scripts/Makefile.common.inc](./common/verif/tb/scripts/Makefile.common.inc)
   - This is required for XSIM and Questa simulations
-  - These libraries can be found in [$AWS_FPGA_REPO_DIR/hdk/common/ip/cl_ip/cl_ip.ip_user_files/sim_scripts](./common/ip/cl_ip/cl_ip.ip_user_files/sim_scripts) followed by `"IP_NAME"/"SIMULATOR"/"IP_NAME".sh`
+  - These libraries can be found in [$AWS_FPGA_REPO_DIR/hdk/common/ip/cl_ip/cl_ip.ip_user_files/sim_scripts](https://github.com/aws/aws-fpga-resources/blob/-/cl_ip/cl_ip.ip_user_files/sim_scripts) followed by `"IP_NAME"/"SIMULATOR"/"IP_NAME".sh`
 - After adding new IP's to [$AWS_FPGA_REPO_DIR/hdk/common/ip](./common/ip) the simulation libraries need to be recompiled
   - Run `make regenerate_sim_libs <XSIM/VCS/QUESTA>=1`
 
@@ -491,7 +491,7 @@ The verif ip_simulation_libraries directory is created during runtime and includ
 
 ### [/ip](./common/ip)
 
-The [ip directory](./common/ip) includes basic IP that is used by CL's.
+The [ip directory](https://github.com/aws/aws-fpga-resources) includes basic IP that is used by CL's.
 
 ### [/lib](./common/lib)
 

hdk/cl/examples/CL_TEMPLATE/README.md

@@ -151,7 +151,7 @@ The result will be a directory containing everything in CL_TEMPLATE (renamed to
 
 All CL design files should be placed under the [design](./design) directory. Please see the [Design](#design) section for information on the CL_TEMPLATE design files.
 
-Users may modify these files and add new ones as their designs grow. Xilinx IP's are available to all CL examples (found under [$AWS_FPGA_REPO_DIR/hdk/common/ip](./../../../common/ip)).
+Users may modify these files and add new ones as their designs grow. Xilinx IP's are available to all CL examples (found under [$AWS_FPGA_REPO_DIR/hdk/common/ip](https://github.com/aws/aws-fpga-resources/tree/Vivado_2024.2-hdk/common/ip)).
 
 ### STEP 3: Develop Design Verification Tests (OPTIONAL)
 
@@ -170,7 +170,7 @@ Or specify an [available simulator](./../../../../README.md#supported-tools-vers
 make CL_TEMPLATE_base_test <SIMULATOR>=1
 ```
 
-This will first generate and compile the simulation libraries required for the requested SIMULATOR. Test results will be stored in the `$CL_DIR/verif/sim/<SIMULATOR>` directory (created upon first simulation run). After adding new IP's to [`$AWS_FPGA_REPO_DIR/hdk/common/ip`](./../../../common/ip) the simulation libraries need to be recompiled: `make regenerate_sim_libs <SIMULATOR>=1`.
+This will first generate and compile the simulation libraries required for the requested SIMULATOR. Test results will be stored in the `$CL_DIR/verif/sim/<SIMULATOR>` directory (created upon first simulation run). After adding new IP's to [`$AWS_FPGA_REPO_DIR/hdk/common/ip`](https://github.com/aws/aws-fpga-resources/tree/Vivado_2024.2-hdk/common/ip) the simulation libraries need to be recompiled: `make regenerate_sim_libs <SIMULATOR>=1`.
 
 #### File List Generation
 
@@ -197,7 +197,7 @@ $CL_DIR/design/CL_TEMPLATE.sv
 
 #### Xilinx/AMD IP Discovery and Compilation
 
-When running your first test, all Xilinx IP's under [$AWS_FPGA_REPO_DIR/hdk/common/ip/cl_ip](./../../../common/ip/cl_ip) are automatically compiled
+When running your first test, all Xilinx IP's under [$AWS_FPGA_REPO_DIR/hdk/common/ip/cl_ip](https://github.com/aws/aws-fpga-resources/tree/Vivado_2024.2-hdk/common/ip/cl_ip) are automatically compiled
 
 - You can find the `xil_defaultlib` library for each simulator in [$AWS_FPGA_REPO_DIR/hdk/common/verif/ip_simulation_libraries/](./../../../common/verif) (created after first simulation run)
 
@@ -207,7 +207,7 @@ If a design adds new IP's, make sure to add the new simulation libraries to `COM
 
 Simulation library names can be found under:
 
-- [$AWS_FPGA_REPO_DIR/hdk/common/ip/cl_ip/cl_ip.ip_user_files/sim_scripts](./../../../common/ip/cl_ip/cl_ip.ip_user_files/sim_scripts)
+- [$AWS_FPGA_REPO_DIR/hdk/common/ip/cl_ip/cl_ip.ip_user_files/sim_scripts](https://github.com/aws/aws-fpga-resources/tree/Vivado_2024.2-hdk/common/ip/cl_ip/cl_ip.ip_user_files/sim_scripts)
 followed by `<IP_NAME>/<SIMULATOR>/<IP_NAME>.sh`
 
 All verification work is located under the [verif](./verif) directory. Please see the [Verification](#verification) section for the CL_TEMPLATE verification details.
@@ -226,7 +226,7 @@ Once design files have been added and tested, constraint and build script update
    - Additional constraint files to be applied during a build
    - Additional tcl scripts to synthesize the design
    - Xilinx IP's utilized in the design
-     - IP's used in AWS example designs can uncommented be in [synth_CL_TEMPLATE.tcl](./build/scripts/synth_CL_TEMPLATE.tcl) and found under [$AWS_FPGA_REPO_DIR/hdk/common/ip/cl_ip](./../../../common/ip/cl_ip)
+     - IP's used in AWS example designs can uncommented be in [synth_CL_TEMPLATE.tcl](./build/scripts/synth_CL_TEMPLATE.tcl) and found under [$AWS_FPGA_REPO_DIR/hdk/common/ip/cl_ip](https://github.com/aws/aws-fpga-resources/tree/Vivado_2024.2-hdk/common/ip/cl_ip)
      - If a design adds new IP's, make sure to add the new `xci` files to the build script [$CL_DIR/build/scripts/synth_CL_TEMPLATE.tcl](./build/scripts/synth_CL_TEMPLATE.tcl)
 3. Run [aws_build_dcp_from_cl.py](./build/scripts/aws_build_dcp_from_cl.py). All defaults can be found by running `aws_build_dcp_from_cl.py --help`
 

hdk/docs/AWS_Shell_Interface_Specification.md

@@ -440,7 +440,7 @@ These steps must be followed to properly connect the monitor interfaces to HBM:
     true
     ```
 
-    **NOTE:** This step can be skipped if the customer uses the `CL_HBM` IP from the [CL examples](./../../hdk/common/ip/cl_ip/). This IP has the `MON_APB` interface enabled and is ready to be integrated to a customer design as-is.
+    **NOTE:** This step can be skipped if the customer uses the `CL_HBM` IP from the [CL examples](https://github.com/aws/aws-fpga-resources/blob/-/cl_ip/cl_ip.gen/sources_1/ip). This IP has the `MON_APB` interface enabled and is ready to be integrated to a customer design as-is.
 
 2. Connect the HBM monitor interface from the shell to the HBM IP. The customer can leave the interface floating if the corresponding HBM rack is not used. For example, the `hbm_apb_p<xx>_1` signals can be left unconnected if HBM rack 1 is unused.
 

hdk/docs/Supported_DDR_Modes.md

@@ -44,7 +44,7 @@ make TEST=${TEST_NAME} USE_AP_64GB_DDR_DIMM=1
 
 ## Required Build Script Modifications
 
-AWS provides following DDR Core IPs as part of Vivado [cl_ip.xpr](./../common/ip/cl_ip/cl_ip.xpr) project. Users are required to enlist one of the following XCI files in the synthesis scripts, depending on the desired DDR configuration and macros defined:
+AWS provides following DDR Core IPs as part of Vivado [cl_ip.xpr](https://github.com/aws/aws-fpga-resources/blob/-/cl_ip/cl_ip.xpr) project. Users are required to enlist one of the following XCI files in the synthesis scripts, depending on the desired DDR configuration and macros defined:
 
 | Macro definition in top level CL | Description                                                        | DDR XCI file to read in synthesis script |
 |----------------------------------|--------------------------------------------------------------------|------------------------------------------|

hdk/docs/Virtual_JTAG_XVC.md

@@ -160,7 +160,7 @@ Guide for debugging designs through Vivado running on a remote machine is coming
 
 ## Embedded Debug Bridge in CL
 
-The [CL_Debug_Bridge](./../common/ip/cl_ip/cl_ip.srcs/sources_1/ip/cl_debug_bridge/cl_debug_bridge.xci) IP must be embedded in the CL design to enable the use of debug cores like ILA and VIO. According to the [AMD user guide](https://docs.amd.com/r/en-US/ug908-vivado-programming-debugging/Debug-Cores-Clocking-Guidelines), the clock of `CL_Debug_Bridge` must be at least 2.5 times faster than the JTAG clock. The JTAG clock frequency is fixed at 31.25 MHz in the F2 shells. Therefore, the frequency of the clock connected to the `CL_Debug_Bridge` should be at least 2.5 x 31.25 MHz = 78.125 MHz. Failure to meet this requirement will result in the debug network not functioning correctly. However, this minimum clock frequency requirement does not apply to the ILA or VIO debug cores or the rest of the CL logic. If the CL design is running on a slower clock from the available clock recipes, care must be taken to ensure that the `CL_Debug_Bridge` is clocked at 78.125 MHz or above.
+The [CL_Debug_Bridge](https://github.com/aws/aws-fpga-resources/blob/-/cl_ip/cl_ip.srcs/sources_1/ip/cl_debug_bridge/cl_debug_bridge.xci) IP must be embedded in the CL design to enable the use of debug cores like ILA and VIO. According to the [AMD user guide](https://docs.amd.com/r/en-US/ug908-vivado-programming-debugging/Debug-Cores-Clocking-Guidelines), the clock of `CL_Debug_Bridge` must be at least 2.5 times faster than the JTAG clock. The JTAG clock frequency is fixed at 31.25 MHz in the F2 shells. Therefore, the frequency of the clock connected to the `CL_Debug_Bridge` should be at least 2.5 x 31.25 MHz = 78.125 MHz. Failure to meet this requirement will result in the debug network not functioning correctly. However, this minimum clock frequency requirement does not apply to the ILA or VIO debug cores or the rest of the CL logic. If the CL design is running on a slower clock from the available clock recipes, care must be taken to ensure that the `CL_Debug_Bridge` is clocked at 78.125 MHz or above.
 
 ```verilog
     //-----------------------------------