Merge commit '840afbde48e9' from llvm.org/main into next

Author: git apple-llvm automerger

clang/lib/Sema/SemaChecking.cpp

@@ -3621,6 +3621,8 @@ static bool isPPC_64Builtin(unsigned BuiltinID) {
   case PPC::BI__builtin_ppc_insert_exp:
   case PPC::BI__builtin_ppc_extract_sig:
   case PPC::BI__builtin_ppc_addex:
+  case PPC::BI__builtin_darn:
+  case PPC::BI__builtin_darn_raw:
     return true;
   }
   return false;
@@ -3804,6 +3806,11 @@ bool Sema::CheckPPCBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
   case PPC::BI__builtin_altivec_vcntmbw:
   case PPC::BI__builtin_altivec_vcntmbd:
     return SemaBuiltinConstantArgRange(TheCall, 1, 0, 1);
+  case PPC::BI__builtin_darn:
+  case PPC::BI__builtin_darn_raw:
+  case PPC::BI__builtin_darn_32:
+    return SemaFeatureCheck(*this, TheCall, "isa-v30-instructions",
+                            diag::err_ppc_builtin_only_on_arch, "9");
 #define CUSTOM_BUILTIN(Name, Intr, Types, Acc) \
   case PPC::BI__builtin_##Name: \
     return SemaBuiltinPPCMMACall(TheCall, Types);

clang/test/CodeGen/builtins-ppc-xlcompat-darn.c

@@ -1,10 +1,13 @@
 // REQUIRES: powerpc-registered-target
 // RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
-// RUN:    -emit-llvm %s -o -  -target-cpu pwr9 | FileCheck %s
+// RUN:    -emit-llvm %s -o -  -target-cpu pwr9 | \
+// RUN:    FileCheck %s --check-prefix=CHECK-64
 // RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \
-// RUN:   -emit-llvm %s -o -  -target-cpu pwr9 | FileCheck %s
+// RUN:   -emit-llvm %s -o -  -target-cpu pwr9 | \
+// RUN:    FileCheck %s --check-prefix=CHECK-64
 // RUN: %clang_cc1 -triple powerpc64-unknown-aix \
-// RUN:    -emit-llvm %s -o -  -target-cpu pwr9 | FileCheck %s
+// RUN:    -emit-llvm %s -o -  -target-cpu pwr9 | \
+// RUN:    FileCheck %s --check-prefix=CHECK-64
 // RUN: %clang_cc1 -triple powerpc-unknown-unknown \
 // RUN:    -emit-llvm %s -o -  -target-cpu pwr9 | FileCheck %s
 // RUN: %clang_cc1 -triple powerpcle-unknown-unknown \
@@ -15,21 +18,23 @@
 // The darn class of builtins are Power 9 and up and only darn_32 works in
 // 32 bit mode.
 
-// CHECK-LABEL: @testdarn(
-// CHECK:         [[TMP0:%.*]] = call i64 @llvm.ppc.darn()
-// CHECK-NEXT:    ret i64 [[TMP0]]
+#ifdef __PPC64__
+// CHECK-64-LABEL: @testdarn(
+// CHECK-64:         [[TMP0:%.*]] = call i64 @llvm.ppc.darn()
+// CHECK-64-NEXT:    ret i64 [[TMP0]]
 //
 long long testdarn(void) {
   return __darn();
 }
 
-// CHECK-LABEL: @testdarn_raw(
-// CHECK:         [[TMP0:%.*]] = call i64 @llvm.ppc.darnraw()
-// CHECK-NEXT:    ret i64 [[TMP0]]
+// CHECK-64-LABEL: @testdarn_raw(
+// CHECK-64:         [[TMP0:%.*]] = call i64 @llvm.ppc.darnraw()
+// CHECK-64-NEXT:    ret i64 [[TMP0]]
 //
 long long testdarn_raw(void) {
   return __darn_raw();
 }
+#endif
 
 // CHECK-LABEL: @testdarn_32(
 // CHECK:         [[TMP0:%.*]] = call i32 @llvm.ppc.darn32()

clang/test/CodeGen/builtins-ppc-xlcompat-error.c

@@ -96,6 +96,14 @@ long long testdivde(long long dividend, long long divisor) {
 unsigned long long testdivdeu(unsigned long long dividend, unsigned long long divisor) {
   return __divdeu(dividend, divisor); //expected-error {{this builtin is only available on 64-bit targets}}
 }
+
+int test_darn() {
+  return __darn(); //expected-error {{this builtin is only available on 64-bit targets}}
+}
+
+int test_darn_raw() {
+  return __darn_raw(); //expected-error {{this builtin is only available on 64-bit targets}}
+}
 #endif
 
 unsigned long test_mfspr(void) {

clang/test/CodeGen/builtins-ppc.c

@@ -36,16 +36,3 @@ void test_builtin_ppc_flm() {
   // CHECK: call double @llvm.ppc.setflm(double %1)
   res = __builtin_setflm(res);
 }
-
-void test_builtin_ppc_darn() {
-  volatile long res;
-  volatile int x;
-  // CHECK: call i64 @llvm.ppc.darn()
-  res = __builtin_darn();
-
-  // CHECK: call i64 @llvm.ppc.darnraw()
-  res = __builtin_darn_raw();
-
-  // CHECK: call i32 @llvm.ppc.darn32()
-  x = __builtin_darn_32();
-}