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Reformat with scalafmt 3.8.6
Executed command: scalafmt --non-interactive
1 parent ba7ed4d commit 77c808e

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8 files changed

+24
-31
lines changed

8 files changed

+24
-31
lines changed

build.sbt

Lines changed: 10 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -70,7 +70,7 @@ lazy val warningSuppression = Seq(
7070
"cat=deprecation&origin=chisel3\\.experimental\\.IntrinsicModule:s",
7171
"cat=deprecation&origin=chisel3\\.ltl.*:s",
7272
"cat=deprecation&origin=chisel3\\.InstanceId:s",
73-
"cat=deprecation&msg=Looking up Modules is deprecated:s",
73+
"cat=deprecation&msg=Looking up Modules is deprecated:s"
7474
).mkString(",")
7575
)
7676

@@ -125,7 +125,7 @@ lazy val firrtlSettings = Seq(
125125
"-language:implicitConversions",
126126
"-Yrangepos", // required by SemanticDB compiler plugin
127127
"-Xsource:3",
128-
"-Xsource-features:infer-override",
128+
"-Xsource-features:infer-override"
129129
),
130130
// Always target Java8 for maximum compatibility
131131
javacOptions ++= Seq("-source", "1.8", "-target", "1.8"),
@@ -317,7 +317,7 @@ lazy val core = (project in file("core"))
317317
"-unchecked",
318318
"-Xcheckinit",
319319
"-Xlint:infer-any",
320-
"-Xsource:3",
320+
"-Xsource:3"
321321
// , "-Xlint:missing-interpolator"
322322
)
323323
)
@@ -343,7 +343,7 @@ lazy val chisel = (project in file("."))
343343
.settings(
344344
// Suppress Scala 3 behavior requiring explicit types on implicit definitions
345345
// Note this must come before the -Wconf is warningSuppression
346-
Test / scalacOptions += "-Wconf:cat=other-implicit-type:s",
346+
Test / scalacOptions += "-Wconf:cat=other-implicit-type:s"
347347
)
348348
.settings(warningSuppression: _*)
349349
.settings(fatalWarningsSettings: _*)
@@ -353,13 +353,12 @@ lazy val chisel = (project in file("."))
353353

354354
def addUnipublishDeps(proj: Project)(deps: Project*): Project = {
355355
def inTestScope(module: ModuleID): Boolean = module.configurations.exists(_ == "test")
356-
deps.foldLeft(proj) {
357-
case (p, dep) =>
358-
p.settings(
359-
libraryDependencies ++= (dep / libraryDependencies).value.filterNot(inTestScope),
360-
Compile / packageBin / mappings ++= (dep / Compile / packageBin / mappings).value,
361-
Compile / packageSrc / mappings ++= (dep / Compile / packageSrc / mappings).value
362-
)
356+
deps.foldLeft(proj) { case (p, dep) =>
357+
p.settings(
358+
libraryDependencies ++= (dep / libraryDependencies).value.filterNot(inTestScope),
359+
Compile / packageBin / mappings ++= (dep / Compile / packageBin / mappings).value,
360+
Compile / packageSrc / mappings ++= (dep / Compile / packageSrc / mappings).value
361+
)
363362
}
364363
}
365364

firrtl/benchmark/src/main/scala/firrtl/benchmark/hot/SerializationBenchmark.scala

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -8,17 +8,17 @@ object SerializationBenchmark extends App {
88
val inputFile = args(0)
99
val warmup = args(1).toInt
1010
val runs = args(2).toInt
11-
val select = if(args.length > 3) args(3) else "o"
11+
val select = if (args.length > 3) args(3) else "o"
1212

1313
val input = filenameToCircuit(inputFile)
1414

15-
if(select == "n") {
15+
if (select == "n") {
1616
println("Benchmarking new Serializer.serialize")
1717
firrtl.benchmark.hot.util.benchmark(warmup, runs)(Serializer.serialize(input))
18-
} else if(select == "o") {
18+
} else if (select == "o") {
1919
println("Benchmarking legacy serialization")
2020
firrtl.benchmark.hot.util.benchmark(warmup, runs)(input.serialize)
21-
} else if(select.startsWith("test")) {
21+
} else if (select.startsWith("test")) {
2222
println("Testing the new serialization against the old one")
2323
val o = input.serialize.split('\n').filterNot(_.trim.isEmpty)
2424
val n = Serializer.serialize(input).split('\n').filterNot(_.trim.isEmpty)
@@ -27,11 +27,11 @@ object SerializationBenchmark extends App {
2727
println(s"Old lines: ${o.length}")
2828
println(s"New lines: ${n.length}")
2929
o.zip(n).zipWithIndex.foreach { case ((ol, nl), ii) =>
30-
if(ol != nl) {
30+
if (ol != nl) {
3131
println(s"❌@$ii OLD: |$ol|")
3232
println(s"❌@$ii NEW: |$nl|")
3333
throw new RuntimeException()
34-
} else if(!silent) {
34+
} else if (!silent) {
3535
println(s"✅ |$ol")
3636
}
3737
}

firrtl/benchmark/src/main/scala/firrtl/benchmark/hot/TransformBenchmark.scala

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -25,4 +25,4 @@ abstract class TransformBenchmark(factory: () => Transform) extends App {
2525

2626
object LowerTypesBenchmark extends TransformBenchmark(() => LowerTypes)
2727

28-
object DedupBenchmark extends TransformBenchmark(() => new DedupModules())
28+
object DedupBenchmark extends TransformBenchmark(() => new DedupModules())

firrtl/benchmark/src/main/scala/firrtl/benchmark/hot/util/package.scala

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,3 @@
1-
21
package firrtl.benchmark.hot
32

43
import firrtl.Utils.time

lit/tests/Converter/Circuit.sc

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4,13 +4,12 @@
44
import chisel3._
55
import chisel3.util.circt.IsX
66

7-
87
// FIRRTL-LABEL: circuit FooModule :
98
// FIRRTL-NEXT: extmodule FooBlackbox :
109
// FIRRTL-NEXT: output o : UInt<1>
1110
// FIRRTL-NEXT: defname = FooBlackbox
1211
class FooBlackbox extends BlackBox {
13-
val io = IO(new Bundle{
12+
val io = IO(new Bundle {
1413
val o = Output(Bool())
1514
})
1615
}

lit/tests/Converter/Module.sc

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
// SPDX-License-Identifier: Apache-2.0
33

44
import chisel3._
5-
import chisel3.experimental.{Analog, attach}
5+
import chisel3.experimental.{attach, Analog}
66
import chisel3.util.SRAM
77

88
// FIRRTL-LABEL: public module Attach :
@@ -76,7 +76,7 @@ class Mem extends Module {
7676
// FIRRTL: invalidate r.data
7777
r.data := DontCare
7878
// FIRRTL: when r.enable :
79-
when (r.enable) {
79+
when(r.enable) {
8080
// FIRRTL-NEXT: infer mport wrPort = mem[r.address], clock
8181
val wrPort = mem(r.address)
8282
// FIRRTL-NEXT: connect r.data, wrPort
@@ -86,7 +86,7 @@ class Mem extends Module {
8686
}
8787

8888
// FIRRTL: when w.enable :
89-
when (w.enable) {
89+
when(w.enable) {
9090
// FIRRTL-NEXT: infer mport wrPort_1 = mem[w.address], clock
9191
val wrPort = mem(w.address)
9292
// FIRRTL-NEXT: connect wrPort_1, w.data

lit/tests/Property/DocExample.sc

Lines changed: 1 addition & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -32,11 +32,7 @@ class CSRDescription extends Class {
3232
}
3333

3434
// A hardware module representing a CSR and its description.
35-
class CSRModule(
36-
csrDescDef: Definition[CSRDescription],
37-
width: Int,
38-
identifierStr: String,
39-
descriptionStr: String)
35+
class CSRModule(csrDescDef: Definition[CSRDescription], width: Int, identifierStr: String, descriptionStr: String)
4036
extends Module {
4137
override def desiredName = identifierStr
4238

project/FirtoolVersionsTable.scala

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -54,8 +54,8 @@ object FirtoolVersionsTable extends App {
5454
val result = allVersions.filter { case (v, _) => v.prerelease ^ release }
5555

5656
val header = Vector("| Chisel Version | Firtool Version |", "| --- | --- |")
57-
val table = (header ++ result.map {
58-
case (sv, fv) => s"| ${sv.serialize} | [$fv](${firtoolGithubLink(fv)}) |"
57+
val table = (header ++ result.map { case (sv, fv) =>
58+
s"| ${sv.serialize} | [$fv](${firtoolGithubLink(fv)}) |"
5959
}).mkString("\n")
6060
table
6161
}

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