implement flw, fsw, fadd.s, fsub.s

Author: Jingqing3948

src/machine/core.cpp

@@ -366,7 +366,9 @@ DecodeState Core::decode(const FetchInterstage &dt) {
                                 .ff_rs = FORWARD_NONE,
                                 .ff_rt = FORWARD_NONE,
                                 .alu_component = (flags & IMF_AMO) ? AluComponent::PASS :
-                                                 (flags & IMF_MUL) ? AluComponent::MUL : AluComponent::ALU,
+                                                 (flags & IMF_MUL) ? AluComponent::MUL :                                                 
+                                                 //  AluComponent::ALU,
+                                                (flags & (IMF_ALU_REQ_RD_F | IMF_ALU_REQ_RS_F | IMF_ALU_REQ_RT_F)) == (IMF_ALU_REQ_RD_F | IMF_ALU_REQ_RS_F | IMF_ALU_REQ_RT_F) ? AluComponent::FALU : AluComponent::ALU,
                                 .aluop = alu_op,
                                 .memctl = mem_ctl,
                                 .num_rs = num_rs,
@@ -376,8 +378,10 @@ DecodeState Core::decode(const FetchInterstage &dt) {
                                 .memwrite = bool(flags & IMF_MEMWRITE),
                                 .alusrc = bool(flags & IMF_ALUSRC),
                                 .regwrite = regwrite,
+                                .regwrite_fp = bool(flags & IMF_ALU_REQ_RD_F),
                                 .alu_req_rs = bool(flags & IMF_ALU_REQ_RS),
                                 .alu_req_rt = bool(flags & IMF_ALU_REQ_RT),
+                                .alu_fp = bool(flags & (IMF_ALU_REQ_RD_F | IMF_ALU_REQ_RS_F | IMF_ALU_REQ_RT_F)), // maybe not correct
                                 .branch_bxx = bool(flags & IMF_BRANCH),
                                 .branch_jal = bool(flags & IMF_JUMP),
                                 .branch_val = bool(flags & IMF_BJ_NOT),
@@ -451,6 +455,8 @@ ExecuteState Core::execute(const DecodeInterstage &dt) {
                  .memread = dt.memread,
                  .memwrite = dt.memwrite,
                  .regwrite = dt.regwrite,
+                 .regwrite_fp = dt.regwrite_fp,
+                 .alu_fp = dt.alu_fp,
                  .is_valid = dt.is_valid,
                  .branch_bxx = dt.branch_bxx,
                  .branch_jal = dt.branch_jal,
@@ -546,13 +552,14 @@ MemoryState Core::memory(const ExecuteInterstage &dt) {
                  .num_rd = dt.num_rd,
                  .memtoreg = memread,
                  .regwrite = regwrite,
+                 .regwrite_fp = dt.regwrite_fp,
                  .is_valid = dt.is_valid,
                  .csr_written = csr_written,
              } };
 }
 
 WritebackState Core::writeback(const MemoryInterstage &dt) {
-    if (dt.regwrite) { regs->write_gp(dt.num_rd, dt.towrite_val); }
+    if (dt.regwrite) { (dt.regwrite_fp) ? regs->write_fp(dt.num_rd, dt.towrite_val) : regs->write_gp(dt.num_rd, dt.towrite_val); }
 
     return WritebackState { WritebackInternalState {
         .inst = (dt.excause == EXCAUSE_NONE)? dt.inst: Instruction::NOP,

src/machine/execute/alu.cpp

@@ -17,6 +17,9 @@ RegisterValue alu_combined_operate(
                              : alu64_operate(op.alu_op, modified, a, b);
     case AluComponent::MUL:
         return (w_operation) ? mul32_operate(op.mul_op, a, b) : mul64_operate(op.mul_op, a, b);
+    case AluComponent::FALU:
+        // return (w_operation) ? alu32f_operate(op.alu_op, modified, a, b) : alu64f_operate(op.alu_op, modified, a, b);
+        return alu32f_operate(op.alu_op, modified, a, b);
     case AluComponent::PASS:
         return a;
     default: qDebug("ERROR, unknown alu component: %hhx", uint8_t(component)); return 0;
@@ -74,6 +77,17 @@ int32_t alu32_operate(AluOp op, bool modified, RegisterValue a, RegisterValue b)
     }
 }
 
+int32_t alu32f_operate(AluOp op, bool modified, RegisterValue a, RegisterValue b) {
+    return alu32_operate(op, modified, a, b);
+    // switch (op) {
+    //     case AluOp::ADD: {
+    //         float result = (a.as_f32()) + ((modified) ? - (b.as_f32()) : (b.as_f32()));
+    //         return *reinterpret_cast<int32_t*>(&result);
+    //     }
+    //     default: qDebug("ERROR, unknown alu operation: %hhx", uint8_t(op)); return 0;
+    // }
+}
+
 int64_t mul64_operate(MulOp op, RegisterValue a, RegisterValue b) {
     switch (op) {
     case MulOp::MUL: return a.as_u64() * b.as_u64();

src/machine/execute/alu.h

@@ -15,6 +15,7 @@ namespace machine {
 enum class AluComponent {
     ALU, //> RV32/64I
     MUL, //> RV32/64M
+    FALU, //> RV32/64F
     PASS, //> Pass operand A without change (used for AMO)
 };
 
@@ -74,6 +75,22 @@ union AluCombinedOp {
  */
 [[gnu::const]] int32_t alu32_operate(AluOp op, bool modified, RegisterValue a, RegisterValue b);
 
+/**
+ * RV32F for OP and OP-IMM instructions and RV64F OP-32 and OP-IMM-32
+ *
+ * ALU conforming to Base Integer Instruction Set, Version 2.0.
+ *
+ * @param op        operation specifier (funct3 in instruction)
+ * @param modified  modifies behavior of ADD (to SUB) and SRL (to SRA)
+ *                  encoded by bit 30 if applicable
+ * @param a         operand 1
+ * @param b         operand 2
+ * @return          result of specified ALU operation (always, no traps)
+ *                  integer type is returned to ensure correct signe extension
+ *                  to arbitrary implementation of RegisterValue
+ */
+[[gnu::const]] int32_t alu32f_operate(AluOp op, bool modified, RegisterValue a, RegisterValue b);
+
 /**
  * RV64 "M" for OP instructions
  *

src/machine/machineconfig.h

@@ -27,7 +27,7 @@ enum ConfigPresets {
 };
 
 constexpr ConfigIsaWord config_isa_word_default = ConfigIsaWord::byChar('E') | ConfigIsaWord::byChar('I') |
-        ConfigIsaWord::byChar('A') |ConfigIsaWord::byChar('M');
+        ConfigIsaWord::byChar('A') | ConfigIsaWord::byChar('M') | ConfigIsaWord::byChar('F');
 
 constexpr ConfigIsaWord config_isa_word_fixed = ConfigIsaWord::byChar('E') | ConfigIsaWord::byChar('I');
 

src/machine/pipeline.h

@@ -102,8 +102,10 @@ struct DecodeInterstage {
     bool memwrite = false;                          // If memory should write input
     bool alusrc = false;      // If second value to alu is immediate value (rt used otherwise)
     bool regwrite = false;    // If output should be written back to register
+    bool regwrite_fp = false; // If output should be written back to floating point register
     bool alu_req_rs = false;  // requires rs value for ALU
     bool alu_req_rt = false;  // requires rt value for ALU or SW
+    bool alu_fp = false;      // ALU operation is floating point
     bool branch_bxx = false;  // branch instruction
     bool branch_jal = false;  // jump
     bool branch_val = false;  // negate branch condition
@@ -170,6 +172,8 @@ struct ExecuteInterstage {
     bool memread = false;
     bool memwrite = false;
     bool regwrite = false;
+    bool regwrite_fp = false;
+    bool alu_fp = false;
     bool is_valid = false;
     bool branch_bxx = false;
     bool branch_jal = false;
@@ -243,6 +247,7 @@ struct MemoryInterstage {
     RegisterId num_rd = 0;
     bool memtoreg = false;
     bool regwrite = false;
+    bool regwrite_fp = false;
     bool is_valid = false;
     bool csr_written = false;
 

src/machine/register_value.h

@@ -79,7 +79,9 @@ class RegisterValue {
 
     [[nodiscard]] constexpr inline int32_t as_i32() const { return (int32_t)data; };
 
-    [[nodiscard]] constexpr inline uint32_t as_u32() const { return (uint32_t)data; };
+    [[nodiscard]] constexpr inline uint32_t as_u32() const { return (uint32_t)data; };    
+    
+    [[nodiscard]] constexpr inline float as_f32() const { union { uint32_t u; float f; } u = {(size_t)data}; return u.f; };
 
     [[nodiscard]] constexpr inline int64_t as_i64() const { return (int64_t)data; };
 
@@ -97,6 +99,8 @@ class RegisterValue {
 
     constexpr explicit operator uint32_t() const { return as_u32(); };
 
+    constexpr explicit operator float() const { return as_f32(); };
+
     constexpr explicit operator int64_t() const { return as_i64(); };
 
     constexpr explicit operator uint64_t() const { return as_u64(); };