Machine: gate TLB updates by root register and privilege mode

Ensure that TLBs are only updated when the root register is set,
and disable TLB updates while running in Machine mode.

Author: nemecad

src/machine/core.cpp

@@ -480,8 +480,8 @@ MemoryState Core::memory(const ExecuteInterstage &dt) {
             excause = memory_special(
                 dt.memctl, dt.inst.rt(), memread, memwrite, towrite_val, dt.val_rt, mem_addr);
         } else if (is_regular_access(dt.memctl)) {
-            if (memwrite) { mem_data->write_ctl(dt.memctl, mem_addr, dt.val_rt); }
-            if (memread) { towrite_val = mem_data->read_ctl(dt.memctl, mem_addr); }
+            if (memwrite) { mem_data->write_ctl(dt.memctl, mem_addr, dt.val_rt, make_ctrl_info(state)); }
+            if (memread) { towrite_val = mem_data->read_ctl(dt.memctl, mem_addr, make_ctrl_info(state)); }
         } else {
             Q_ASSERT(dt.memctl == AC_NONE);
             // AC_NONE is memory NOP

src/machine/core.h

@@ -60,6 +60,11 @@ class Core : public QObject {
     bool get_step_over_exception(enum ExceptionCause excause) const;
     void set_current_privilege(CSR::PrivilegeLevel privilege);
     CSR::PrivilegeLevel get_current_privilege() const;
+    static inline uint32_t make_ctrl_info(const CoreState &st) {
+        uint32_t priv = static_cast<uint32_t>(st.current_privilege()) & 0x3u;
+        uint32_t asid = static_cast<uint32_t>(st.current_asid()) & 0x1FFu;
+        return priv | (asid << 2);
+    }
 
     /**
      * Abstracts XLEN from code flow. XLEN core will obtain XLEN value from register value.

src/machine/core/core_state.h

@@ -19,6 +19,7 @@ struct CoreState {
     uint32_t stall_count = 0;
     uint32_t cycle_count = 0;
     unsigned current_privilege_u = static_cast<unsigned>(CSR::PrivilegeLevel::MACHINE);
+    unsigned current_asid_u = 0u;
 
     [[nodiscard]] CSR::PrivilegeLevel current_privilege() const noexcept {
         return static_cast<CSR::PrivilegeLevel>(current_privilege_u);
@@ -27,6 +28,14 @@ struct CoreState {
     void set_current_privilege(CSR::PrivilegeLevel p) noexcept {
         current_privilege_u = static_cast<unsigned>(p);
     }
+
+    [[nodiscard]] uint16_t current_asid() const noexcept {
+        return static_cast<uint16_t>(current_asid_u & 0x1FFu);
+    }
+
+    void set_current_asid(uint16_t a) noexcept {
+        current_asid_u = static_cast<unsigned>(a & 0x1FFu);
+    }
 };
 
 } // namespace machine

src/machine/machine.cpp

@@ -72,9 +72,11 @@ Machine::Machine(MachineConfig config, bool load_symtab, bool load_executable)
         cch_program, PROGRAM, machine_config.access_tlb_program(), machine_config.get_vm_enabled());
     tlb_data = new TLB(
         cch_data, DATA, machine_config.access_tlb_data(), machine_config.get_vm_enabled());
-    controlst->write_internal(CSR::Id::SATP, 0);
     tlb_program->on_csr_write(CSR::Id::SATP, 0);
     tlb_data->on_csr_write(CSR::Id::SATP, 0);
+    connect(controlst, &CSR::ControlState::write_signal, tlb_program, &machine::TLB::on_csr_write);
+    connect(controlst, &CSR::ControlState::write_signal, tlb_data, &machine::TLB::on_csr_write);
+    controlst->write_internal(CSR::Id::SATP, 0);
 
     predictor = new BranchPredictor(
         machine_config.get_bp_enabled(), machine_config.get_bp_type(),

src/machine/memory/frontend_memory.cpp

@@ -37,7 +37,7 @@ uint64_t FrontendMemory::read_u64(Address address, AccessEffects type) const {
     return read_generic<uint64_t>(address, type);
 }
 
-void FrontendMemory::write_ctl(enum AccessControl ctl, Address offset, RegisterValue value) {
+void FrontendMemory::write_ctl(enum AccessControl ctl, Address offset, RegisterValue value,  uint32_t ctrl_info ) {
     switch (ctl) {
     case AC_NONE: {
         break;
@@ -68,9 +68,10 @@ void FrontendMemory::write_ctl(enum AccessControl ctl, Address offset, RegisterV
             QString::number(ctl));
     }
     }
+    handle_control_signal(ctrl_info);
 }
 
-RegisterValue FrontendMemory::read_ctl(enum AccessControl ctl, Address address) const {
+RegisterValue FrontendMemory::read_ctl(enum AccessControl ctl, Address address,  uint32_t ctrl_info ) const {
     switch (ctl) {
     case AC_NONE: return 0;
     case AC_I8: return (int8_t)read_u8(address);
@@ -87,6 +88,7 @@ RegisterValue FrontendMemory::read_ctl(enum AccessControl ctl, Address address)
             QString::number(ctl));
     }
     }
+    const_cast<FrontendMemory *>(this)->handle_control_signal(ctrl_info);
 }
 
 void FrontendMemory::sync() {}

src/machine/memory/frontend_memory.h

@@ -11,6 +11,8 @@
 #include <QObject>
 #include <cstdint>
 
+#include "csr/address.h"
+
 // Shortcut for enum class values, type is obvious from context.
 using ae = machine::AccessEffects;
 
@@ -68,7 +70,7 @@ class FrontendMemory : public QObject {
      * REGULAR.
      * @param control_signal    CPU control unit signal
      */
-    void write_ctl(AccessControl control_signal, Address destination, RegisterValue value);
+    void write_ctl(AccessControl control_signal, Address destination, RegisterValue value,  uint32_t ctrl_info = 0);
 
     /**
      * Read with size specified by the CPU control unit.
@@ -77,12 +79,21 @@ class FrontendMemory : public QObject {
      * ae::REGULAR.
      * @param control_signal    CPU control unit signal
      */
-    [[nodiscard]] RegisterValue read_ctl(enum AccessControl ctl, Address source) const;
+    [[nodiscard]] RegisterValue read_ctl(enum AccessControl ctl, Address source,  uint32_t ctrl_info = 0) const;
+
+    virtual void handle_control_signal(uint32_t ctrl_info) { Q_UNUSED(ctrl_info); }
 
     virtual void sync();
     [[nodiscard]] virtual LocationStatus location_status(Address address) const;
     [[nodiscard]] virtual uint32_t get_change_counter() const = 0;
 
+    static inline CSR::PrivilegeLevel unpack_priv(uint32_t token) {
+        return static_cast<CSR::PrivilegeLevel>(token & 0x3u);
+    }
+    static inline uint16_t unpack_asid(uint32_t token) {
+        return static_cast<uint16_t>((token >> 2) & 0x1FFu);
+    }
+
     /**
      * Write byte sequence to memory
      *

src/machine/memory/tlb/tlb.cpp

@@ -3,7 +3,6 @@
 #include "csr/controlstate.h"
 #include "machine.h"
 #include "memory/virtual/page_table_walker.h"
-#include "memory/virtual/sv32.h"
 
 LOG_CATEGORY("machine.TLB");
 
@@ -64,6 +63,8 @@ void TLB::on_csr_write(size_t internal_id, RegisterValue val) {
     update_all_statistics();
 }
 
+
+
 void TLB::flush_single(VirtualAddress va, uint16_t asid) {
     uint64_t vpn = va.get_raw() >> 12;
     size_t s = set_index(vpn);
@@ -111,7 +112,9 @@ void TLB::sync() {
 Address TLB::translate_virtual_to_physical(Address vaddr) {
     uint64_t virt = vaddr.get_raw();
 
-    if (!vm_enabled) { return vaddr; }
+    if (!vm_enabled || !translation_enabled || is_in_uncached_area(vaddr)) {
+        return vaddr;
+    }
 
     constexpr unsigned PAGE_SHIFT = 12;
     constexpr uint64_t PAGE_MASK = (1ULL << PAGE_SHIFT) - 1;
@@ -191,6 +194,20 @@ bool TLB::reverse_lookup(Address paddr, VirtualAddress &out_va) const {
     }
     return false;
 }
+
+void TLB::handle_control_signal(uint32_t ctrl_info) {
+    CSR::PrivilegeLevel priv = unpack_priv(ctrl_info);
+    uint16_t asid = unpack_asid(ctrl_info);
+
+    bool satp_mode_on = is_mode_enabled_in_satp(current_satp_raw);
+    bool should_translate = vm_enabled && satp_mode_on && (priv != CSR::PrivilegeLevel::MACHINE);
+
+    if (translation_enabled != should_translate) {
+        translation_enabled = should_translate;
+        LOG("TLB: translation_enabled -> %d (ASID=%u)", (int)translation_enabled, asid);
+    }
+}
+
 bool TLB::is_in_uncached_area(Address source) const {
     return (source >= uncached_start && source <= uncached_last);
 }

src/machine/memory/tlb/tlb.h

@@ -2,6 +2,7 @@
 #define TLB_H
 
 #include "common/logging.h"
+#include "csr/address.h"
 #include "memory/frontend_memory.h"
 #include "memory/virtual/sv32.h"
 #include "memory/virtual/virtual_address.h"
@@ -67,6 +68,7 @@ class TLB : public FrontendMemory {
 
     void reset();
     void update_all_statistics();
+    void handle_control_signal(uint32_t ctrl_info) override;
 
 signals:
     void tlb_update(
@@ -98,6 +100,7 @@ class TLB : public FrontendMemory {
     TLBType type;
     const TLBConfig tlb_config;
     uint32_t current_satp_raw = 0;
+    bool translation_enabled = false;
     const bool vm_enabled;
 
     size_t num_sets_;
@@ -122,6 +125,7 @@ class TLB : public FrontendMemory {
     WriteResult translate_and_write(Address dst, const void *src, size_t sz, WriteOptions opts);
     ReadResult translate_and_read(void *dst, Address src, size_t sz, ReadOptions opts);
     inline size_t set_index(uint64_t vpn) const { return vpn & (num_sets_ - 1); }
+    inline bool is_mode_enabled_in_satp(uint32_t satp_raw) { return (satp_raw & (1u << 31)) != 0; }
 };
 
 } // namespace machine