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Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging
pc,pci,virtio: fixes, features Fixes all over the place. PXB support for ARM. boot index for vhost-user-fs. Signed-off-by: Michael S. Tsirkin <[email protected]> # gpg: Signature made Sun 17 Jan 2021 11:44:55 GMT # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469 # gpg: issuer "[email protected]" # gpg: Good signature from "Michael S. Tsirkin <[email protected]>" [full] # gpg: aka "Michael S. Tsirkin <[email protected]>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * remotes/mst/tags/for_upstream: acpi: Update _DSM method in expected files acpi: Enable pxb unit-test for ARM virt machine Kconfig: Compile PXB for ARM_VIRT acpi/gpex: Exclude pxb's resources from PCI0 acpi/gpex: Inform os to keep firmware resource map acpi: Add addr offset in build_crs acpi: Fix unmatched expected DSDT.pxb file acpi: Allow DSDT acpi table changes vhost-user-fs: add the "bootindex" property pci/shpc: don't push attention button when ejecting powered-off device Signed-off-by: Peter Maydell <[email protected]>
2 parents 825a215 + ccee1a8 commit e0cbcf1

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-41
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15 files changed

+94
-41
lines changed

‎hw/acpi/aml-build.c‎

Lines changed: 10 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -2076,7 +2076,9 @@ void build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog)
20762076
tpm2_ptr, "TPM2", table_data->len - tpm2_start, 4, NULL, NULL);
20772077
}
20782078

2079-
Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set)
2079+
Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set, uint32_t io_offset,
2080+
uint32_t mmio32_offset, uint64_t mmio64_offset,
2081+
uint16_t bus_nr_offset)
20802082
{
20812083
Aml *crs = aml_resource_template();
20822084
CrsRangeSet temp_range_set;
@@ -2189,10 +2191,10 @@ Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set)
21892191
for (i = 0; i < temp_range_set.io_ranges->len; i++) {
21902192
entry = g_ptr_array_index(temp_range_set.io_ranges, i);
21912193
aml_append(crs,
2192-
aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
2193-
AML_POS_DECODE, AML_ENTIRE_RANGE,
2194-
0, entry->base, entry->limit, 0,
2195-
entry->limit - entry->base + 1));
2194+
aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED,
2195+
AML_POS_DECODE, AML_ENTIRE_RANGE,
2196+
0, entry->base, entry->limit, io_offset,
2197+
entry->limit - entry->base + 1));
21962198
crs_range_insert(range_set->io_ranges, entry->base, entry->limit);
21972199
}
21982200

@@ -2205,7 +2207,7 @@ Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set)
22052207
aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
22062208
AML_MAX_FIXED, AML_NON_CACHEABLE,
22072209
AML_READ_WRITE,
2208-
0, entry->base, entry->limit, 0,
2210+
0, entry->base, entry->limit, mmio32_offset,
22092211
entry->limit - entry->base + 1));
22102212
crs_range_insert(range_set->mem_ranges, entry->base, entry->limit);
22112213
}
@@ -2217,7 +2219,7 @@ Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set)
22172219
aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
22182220
AML_MAX_FIXED, AML_NON_CACHEABLE,
22192221
AML_READ_WRITE,
2220-
0, entry->base, entry->limit, 0,
2222+
0, entry->base, entry->limit, mmio64_offset,
22212223
entry->limit - entry->base + 1));
22222224
crs_range_insert(range_set->mem_64bit_ranges,
22232225
entry->base, entry->limit);
@@ -2230,7 +2232,7 @@ Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set)
22302232
0,
22312233
pci_bus_num(host->bus),
22322234
max_bus,
2233-
0,
2235+
bus_nr_offset,
22342236
max_bus - pci_bus_num(host->bus) + 1));
22352237

22362238
return crs;

‎hw/i386/acpi-build.c‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1360,7 +1360,8 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
13601360
}
13611361

13621362
aml_append(dev, build_prt(false));
1363-
crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set);
1363+
crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set,
1364+
0, 0, 0, 0);
13641365
aml_append(dev, aml_name_decl("_CRS", crs));
13651366
aml_append(scope, dev);
13661367
aml_append(dsdt, scope);

‎hw/pci-bridge/Kconfig‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@ config PCIE_PORT
55

66
config PXB
77
bool
8-
default y if Q35
8+
default y if Q35 || ARM_VIRT
99

1010
config XIO3130
1111
bool

‎hw/pci-host/gpex-acpi.c‎

Lines changed: 63 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -112,10 +112,26 @@ static void acpi_dsdt_add_pci_osc(Aml *dev)
112112
UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D");
113113
ifctx = aml_if(aml_equal(aml_arg(0), UUID));
114114
ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0)));
115-
uint8_t byte_list[1] = {1};
116-
buf = aml_buffer(1, byte_list);
115+
uint8_t byte_list[] = {
116+
0x1 << 0 /* support for functions other than function 0 */ |
117+
0x1 << 5 /* support for function 5 */
118+
};
119+
buf = aml_buffer(ARRAY_SIZE(byte_list), byte_list);
117120
aml_append(ifctx1, aml_return(buf));
118121
aml_append(ifctx, ifctx1);
122+
123+
/*
124+
* PCI Firmware Specification 3.1
125+
* 4.6.5. _DSM for Ignoring PCI Boot Configurations
126+
*/
127+
/* Arg2: Function Index: 5 */
128+
ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(5)));
129+
/*
130+
* 0 - The operating system must not ignore the PCI configuration that
131+
* firmware has done at boot time.
132+
*/
133+
aml_append(ifctx1, aml_return(aml_int(0)));
134+
aml_append(ifctx, ifctx1);
119135
aml_append(method, ifctx);
120136

121137
byte_list[0] = 0;
@@ -130,6 +146,8 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
130146
Aml *method, *crs, *dev, *rbuf;
131147
PCIBus *bus = cfg->bus;
132148
CrsRangeSet crs_range_set;
149+
CrsRangeEntry *entry;
150+
int i;
133151

134152
/* start to construct the tables for pxb */
135153
crs_range_set_init(&crs_range_set);
@@ -168,15 +186,15 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
168186
* 1. The resources the pci-brige/pcie-root-port need.
169187
* 2. The resources the devices behind pxb need.
170188
*/
171-
crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set);
189+
crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set,
190+
cfg->pio.base, 0, 0, 0);
172191
aml_append(dev, aml_name_decl("_CRS", crs));
173192

174193
acpi_dsdt_add_pci_osc(dev);
175194

176195
aml_append(scope, dev);
177196
}
178197
}
179-
crs_range_set_free(&crs_range_set);
180198

181199
/* tables for the main */
182200
dev = aml_device("%s", "PCI0");
@@ -194,36 +212,55 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
194212
aml_append(method, aml_return(aml_int(cfg->ecam.base)));
195213
aml_append(dev, method);
196214

215+
/*
216+
* At this point crs_range_set has all the ranges used by pci
217+
* busses *other* than PCI0. These ranges will be excluded from
218+
* the PCI0._CRS.
219+
*/
197220
rbuf = aml_resource_template();
198221
aml_append(rbuf,
199222
aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
200223
0x0000, 0x0000, nr_pcie_buses - 1, 0x0000,
201224
nr_pcie_buses));
202225
if (cfg->mmio32.size) {
203-
aml_append(rbuf,
204-
aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
205-
AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
206-
cfg->mmio32.base,
207-
cfg->mmio32.base + cfg->mmio32.size - 1,
208-
0x0000,
209-
cfg->mmio32.size));
226+
crs_replace_with_free_ranges(crs_range_set.mem_ranges,
227+
cfg->mmio32.base,
228+
cfg->mmio32.base + cfg->mmio32.size - 1);
229+
for (i = 0; i < crs_range_set.mem_ranges->len; i++) {
230+
entry = g_ptr_array_index(crs_range_set.mem_ranges, i);
231+
aml_append(rbuf,
232+
aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
233+
AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
234+
entry->base, entry->limit,
235+
0x0000, entry->limit - entry->base + 1));
236+
}
210237
}
211238
if (cfg->pio.size) {
212-
aml_append(rbuf,
213-
aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
214-
AML_ENTIRE_RANGE, 0x0000, 0x0000,
215-
cfg->pio.size - 1,
216-
cfg->pio.base,
217-
cfg->pio.size));
239+
crs_replace_with_free_ranges(crs_range_set.io_ranges,
240+
0x0000,
241+
cfg->pio.size - 1);
242+
for (i = 0; i < crs_range_set.io_ranges->len; i++) {
243+
entry = g_ptr_array_index(crs_range_set.io_ranges, i);
244+
aml_append(rbuf,
245+
aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
246+
AML_ENTIRE_RANGE, 0x0000, entry->base,
247+
entry->limit, cfg->pio.base,
248+
entry->limit - entry->base + 1));
249+
}
218250
}
219251
if (cfg->mmio64.size) {
220-
aml_append(rbuf,
221-
aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
222-
AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
223-
cfg->mmio64.base,
224-
cfg->mmio64.base + cfg->mmio64.size - 1,
225-
0x0000,
226-
cfg->mmio64.size));
252+
crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges,
253+
cfg->mmio64.base,
254+
cfg->mmio64.base + cfg->mmio64.size - 1);
255+
for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) {
256+
entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i);
257+
aml_append(rbuf,
258+
aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
259+
AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
260+
entry->base,
261+
entry->limit, 0x0000,
262+
entry->limit - entry->base + 1));
263+
}
227264
}
228265
aml_append(dev, aml_name_decl("_CRS", rbuf));
229266

@@ -242,4 +279,6 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
242279
aml_append(dev_res0, aml_name_decl("_CRS", crs));
243280
aml_append(dev, dev_res0);
244281
aml_append(scope, dev);
282+
283+
crs_range_set_free(&crs_range_set);
245284
}

‎hw/pci/shpc.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -300,7 +300,6 @@ static void shpc_slot_command(SHPCDevice *shpc, uint8_t target,
300300
shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_EMPTY,
301301
SHPC_SLOT_STATUS_PRSNT_MASK);
302302
shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
303-
SHPC_SLOT_EVENT_BUTTON |
304303
SHPC_SLOT_EVENT_MRL |
305304
SHPC_SLOT_EVENT_PRESENCE;
306305
}
@@ -566,7 +565,6 @@ void shpc_device_unplug_request_cb(HotplugHandler *hotplug_dev,
566565
return;
567566
}
568567

569-
shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |= SHPC_SLOT_EVENT_BUTTON;
570568
state = shpc_get_status(shpc, slot, SHPC_SLOT_STATE_MASK);
571569
led = shpc_get_status(shpc, slot, SHPC_SLOT_PWR_LED_MASK);
572570
if (state == SHPC_STATE_DISABLED && led == SHPC_LED_OFF) {
@@ -577,6 +575,8 @@ void shpc_device_unplug_request_cb(HotplugHandler *hotplug_dev,
577575
shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
578576
SHPC_SLOT_EVENT_MRL |
579577
SHPC_SLOT_EVENT_PRESENCE;
578+
} else {
579+
shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |= SHPC_SLOT_EVENT_BUTTON;
580580
}
581581
shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_66);
582582
shpc_interrupt_update(pci_hotplug_dev);

‎hw/virtio/vhost-user-fs-pci.c‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -68,6 +68,8 @@ static void vhost_user_fs_pci_instance_init(Object *obj)
6868

6969
virtio_instance_init_common(obj, &dev->vdev, sizeof(dev->vdev),
7070
TYPE_VHOST_USER_FS);
71+
object_property_add_alias(obj, "bootindex", OBJECT(&dev->vdev),
72+
"bootindex");
7173
}
7274

7375
static const VirtioPCIDeviceTypeInfo vhost_user_fs_pci_info = {

‎hw/virtio/vhost-user-fs.c‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -22,6 +22,7 @@
2222
#include "qemu/error-report.h"
2323
#include "hw/virtio/vhost-user-fs.h"
2424
#include "monitor/monitor.h"
25+
#include "sysemu/sysemu.h"
2526

2627
static void vuf_get_config(VirtIODevice *vdev, uint8_t *config)
2728
{
@@ -279,6 +280,14 @@ static Property vuf_properties[] = {
279280
DEFINE_PROP_END_OF_LIST(),
280281
};
281282

283+
static void vuf_instance_init(Object *obj)
284+
{
285+
VHostUserFS *fs = VHOST_USER_FS(obj);
286+
287+
device_add_bootindex_property(obj, &fs->bootindex, "bootindex",
288+
"/filesystem@0", DEVICE(obj));
289+
}
290+
282291
static void vuf_class_init(ObjectClass *klass, void *data)
283292
{
284293
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -300,6 +309,7 @@ static const TypeInfo vuf_info = {
300309
.name = TYPE_VHOST_USER_FS,
301310
.parent = TYPE_VIRTIO_DEVICE,
302311
.instance_size = sizeof(VHostUserFS),
312+
.instance_init = vuf_instance_init,
303313
.class_init = vuf_class_init,
304314
};
305315

‎include/hw/acpi/aml-build.h‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -452,7 +452,9 @@ void crs_replace_with_free_ranges(GPtrArray *ranges,
452452
void crs_range_set_init(CrsRangeSet *range_set);
453453
void crs_range_set_free(CrsRangeSet *range_set);
454454

455-
Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set);
455+
Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set, uint32_t io_offset,
456+
uint32_t mmio32_offset, uint64_t mmio64_offset,
457+
uint16_t bus_nr_offset);
456458

457459
void build_srat_memory(AcpiSratMemoryAffinity *numamem, uint64_t base,
458460
uint64_t len, int node, MemoryAffinityFlags flags);

‎include/hw/virtio/vhost-user-fs.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -39,6 +39,7 @@ struct VHostUserFS {
3939
VhostUserState vhost_user;
4040
VirtQueue **req_vqs;
4141
VirtQueue *hiprio_vq;
42+
int32_t bootindex;
4243

4344
/*< public >*/
4445
};

‎tests/data/acpi/microvm/DSDT.pcie‎

8 Bytes
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