From 28037d3bc4f1922c1b50cf04978f62c9d6a4d96a Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 4 Sep 2025 16:26:40 +0530 Subject: [PATCH 1/2] schemas: pci: Add W_DISABLE1# and VIO supply properties for M.2 slot As per M.2 spec r4.0, add below PCI specific properties to describe a M.2 slot: 1. w-disable1-gpios: Specifies the GPIO controlled connection to W_DISABLE1# signal used for disabling the wireless radio on the M.2 card. When present, this signal is used to disable WLAN radio of the M.2 card. The spec defines one more signal, W_DISABLE2#, but that is applicable for Bluetooth only. Hence, not added here. 2. vio1v8-supply - Specifies the phandle to the VIO 1.8v regulator which supplies power to the Adapter I/O buffer circuitry operating at 1.8 V sideband signaling. Signed-off-by: Manivannan Sadhasivam --- dtschema/schemas/pci/pci-bus-common.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/dtschema/schemas/pci/pci-bus-common.yaml b/dtschema/schemas/pci/pci-bus-common.yaml index a39fafc..716f1ae 100644 --- a/dtschema/schemas/pci/pci-bus-common.yaml +++ b/dtschema/schemas/pci/pci-bus-common.yaml @@ -146,6 +146,10 @@ properties: description: GPIO controlled connection to WAKE# signal maxItems: 1 + w-disable1-gpios: + description: GPIO controlled connection to W_DISABLE1# signal + maxItems: 1 + slot-power-limit-milliwatt: description: If present, specifies slot power limit in milliwatts. @@ -179,6 +183,9 @@ properties: vpcie3v3aux-supply: description: 3.3v AUX regulator phandle for the slot + vio1v8-supply: + description: 1.8v VIO regulator phandle for the slot + eq-presets-8gts: description: Contains the equalization preset values for PCIe data rates 8.0 GT/s. From 22d8095f83b515a8cb6cdeaaf88a9175beb1bfe5 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 4 Sep 2025 16:42:30 +0530 Subject: [PATCH 2/2] schemas: pci: bridge: Remove unused 'supports-d3' property This property was added to specify that the PCI bridge supports D3 state, as it cannot be discovered by the OS using PMCSR registers. This was added to use it with the PCI subsystem of Linux Kernel. But this property was never used, as the PCI subsystem in Linux Kernel decided to assume that all PCI bridges of the DT based platforms supports transitioning to D3 state by default. So remove this unused property. Signed-off-by: Manivannan Sadhasivam --- dtschema/schemas/pci/pci-pci-bridge.yaml | 6 ------ 1 file changed, 6 deletions(-) diff --git a/dtschema/schemas/pci/pci-pci-bridge.yaml b/dtschema/schemas/pci/pci-pci-bridge.yaml index 7933e01..91ad41f 100644 --- a/dtschema/schemas/pci/pci-pci-bridge.yaml +++ b/dtschema/schemas/pci/pci-pci-bridge.yaml @@ -28,10 +28,4 @@ properties: contains: const: pciclass,0604 - supports-d3: - description: - If present, this property specifies that the bridge supports transitioning - to D3 states. - type: boolean - additionalProperties: true