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Sorry, I missed this when you originally posted it. My understanding of the limitation of integer dividers was that the MCLK signal would then wind up with either rising-to-rising or falling-to-falling periods that were too fast/slow (i.e. the jitter would cause an effective frequency increase for a cycle) which caused the DACs to misbehave. There's a discussion in #1065 about this leading to the integer-only division... |
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Hi @earlephilhower,
I have found a way to improve the sample rate from 48.046 kHz to 48.0000 kHz, and this is really important in my SDR application. It might be useful to others, and it involves modifying your I2S.cpp and I2S.h. The changes I made to I2S.cpp were:
and to I2S.h
I could have used 115200 for I2SSYSCLK_8, too.
I am using the PCM1808 ADC and measuring the frequency of LRCK and SCKI. SCKI should be 12.288 MHz, and I get 12.2879 MHz for it. It might create a bit more jitter, but I don't have the problem requiring me to discard samples regularly, which is probably worse.
I measured three more Chinese Pico clones. The other one was a real Pico W. For SCKI, the frequencies were 12.2885, 12.2886, and 12.2887 MHz, and the clones are all more than an order of magnitude better than the old result. The real Pico W is at least two orders of magnitude better, and its error is on the verge of not being measurable by my humble oscilloscope.
Do you see anything wrong with this?
Rob
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