wip: pci transport

Signed-off-by: Babis Chalios <[email protected]>

Author: bchalios

src/vmm/src/devices/virtio/transport/pci/common_config.rs

@@ -16,7 +16,7 @@ use vm_memory::GuestAddress;
 
 use crate::devices::virtio::device::VirtioDevice;
 use crate::devices::virtio::queue::Queue;
-use crate::logger::{debug, error, info, trace, warn};
+use crate::logger::warn;
 pub const VIRTIO_PCI_COMMON_CONFIG_ID: &str = "virtio_pci_common_config";
 
 #[derive(Debug, Clone, Serialize, Deserialize)]
@@ -176,7 +176,10 @@ impl VirtioPciCommonConfig {
                 let v = self.read_common_config_qword(offset);
                 LittleEndian::write_u64(data, v);
             }
-            _ => error!("invalid data length for virtio read: len {}", data.len()),
+            _ => warn!(
+                "pci: invalid data length for virtio read: len {}",
+                data.len()
+            ),
         }
     }
 
@@ -196,35 +199,35 @@ impl VirtioPciCommonConfig {
                 LittleEndian::read_u64(data),
                 device.lock().unwrap().queues_mut(),
             ),
-            _ => error!("invalid data length for virtio write: len {}", data.len()),
+            _ => warn!(
+                "pci: invalid data length for virtio write: len {}",
+                data.len()
+            ),
         }
     }
 
     fn read_common_config_byte(&self, offset: u64) -> u8 {
-        debug!("read_common_config_byte: offset 0x{:x}", offset);
         // The driver is only allowed to do aligned, properly sized access.
         match offset {
             0x14 => self.driver_status,
             0x15 => self.config_generation,
             _ => {
-                warn!("invalid virtio config byte read: 0x{:x}", offset);
+                warn!("pci: invalid virtio config byte read: 0x{:x}", offset);
                 0
             }
         }
     }
 
     fn write_common_config_byte(&mut self, offset: u64, value: u8) {
-        debug!("write_common_config_byte: offset 0x{offset:x}: {value:x}");
         match offset {
             0x14 => self.driver_status = value,
             _ => {
-                warn!("invalid virtio config byte write: 0x{:x}", offset);
+                warn!("pci: invalid virtio config byte write: 0x{:x}", offset);
             }
         }
     }
 
     fn read_common_config_word(&self, offset: u64, queues: &[Queue]) -> u16 {
-        debug!("read_common_config_word: offset 0x{:x}", offset);
         match offset {
             0x10 => self.msix_config.load(Ordering::Acquire),
             0x12 => queues.len().try_into().unwrap(), // num_queues
@@ -246,14 +249,13 @@ impl VirtioPciCommonConfig {
             0x1c => u16::from(self.with_queue(queues, |q| q.ready).unwrap_or(false)),
             0x1e => self.queue_select, // notify_off
             _ => {
-                warn!("invalid virtio register word read: 0x{:x}", offset);
+                warn!("pci: invalid virtio register word read: 0x{:x}", offset);
                 0
             }
         }
     }
 
     fn write_common_config_word(&mut self, offset: u64, value: u16, queues: &mut [Queue]) {
-        debug!("write_common_config_word: offset 0x{:x}", offset);
         match offset {
             0x10 => self.msix_config.store(value, Ordering::Release),
             0x16 => self.queue_select = value,
@@ -274,13 +276,12 @@ impl VirtioPciCommonConfig {
                 q.ready = value == 1;
             }),
             _ => {
-                warn!("invalid virtio register word write: 0x{:x}", offset);
+                warn!("pci: invalid virtio register word write: 0x{:x}", offset);
             }
         }
     }
 
     fn read_common_config_dword(&self, offset: u64, device: Arc<Mutex<dyn VirtioDevice>>) -> u32 {
-        debug!("read_common_config_dword: offset 0x{:x}", offset);
         match offset {
             0x00 => self.device_feature_select,
             0x04 => {
@@ -296,7 +297,7 @@ impl VirtioPciCommonConfig {
             }
             0x08 => self.driver_feature_select,
             _ => {
-                warn!("invalid virtio register dword read: 0x{:x}", offset);
+                warn!("pci: invalid virtio register dword read: 0x{:x}", offset);
                 0
             }
         }
@@ -308,7 +309,6 @@ impl VirtioPciCommonConfig {
         value: u32,
         device: Arc<Mutex<dyn VirtioDevice>>,
     ) {
-        debug!("write_common_config_dword: offset 0x{:x}", offset);
         fn hi(v: &mut GuestAddress, x: u32) {
             *v = (*v & 0xffff_ffff) | (u64::from(x) << 32)
         }
@@ -342,19 +342,16 @@ impl VirtioPciCommonConfig {
                 hi(&mut q.used_ring_address, value)
             }),
             _ => {
-                warn!("invalid virtio register dword write: 0x{:x}", offset);
+                warn!("pci: invalid virtio register dword write: 0x{:x}", offset);
             }
         }
     }
 
     fn read_common_config_qword(&self, _offset: u64) -> u64 {
-        debug!("read_common_config_qword: offset 0x{:x}", _offset);
         0 // Assume the guest has no reason to read write-only registers.
     }
 
     fn write_common_config_qword(&mut self, offset: u64, value: u64, queues: &mut [Queue]) {
-        debug!("write_common_config_qword: offset 0x{:x}", offset);
-
         let low = Some((value & 0xffff_ffff) as u32);
         let high = Some((value >> 32) as u32);
 
@@ -363,7 +360,7 @@ impl VirtioPciCommonConfig {
             0x28 => self.with_queue_mut(queues, |q| q.avail_ring_address.0 = value),
             0x30 => self.with_queue_mut(queues, |q| q.used_ring_address.0 = value),
             _ => {
-                warn!("invalid virtio register qword write: 0x{:x}", offset);
+                warn!("pci: invalid virtio register qword write: 0x{:x}", offset);
             }
         }
     }