From 15f754ba7b018949cfb3bb42d39cda2841504a2a Mon Sep 17 00:00:00 2001 From: Viktor Khristenko Date: Mon, 27 Jan 2020 16:38:22 +0100 Subject: [PATCH 1/3] add ip_handler_top decl in header and rename the test file to force make csim pass by default --- hls/ip_handler/ip_handler.hpp | 10 +++++++ hls/ip_handler/newtcp.in | 51 +++++++++++++++++++++++++++++++++++ 2 files changed, 61 insertions(+) create mode 100644 hls/ip_handler/newtcp.in diff --git a/hls/ip_handler/ip_handler.hpp b/hls/ip_handler/ip_handler.hpp index 9374e78..395d53a 100755 --- a/hls/ip_handler/ip_handler.hpp +++ b/hls/ip_handler/ip_handler.hpp @@ -47,3 +47,13 @@ void ip_handler(hls::stream >& s_axis_raw, hls::stream >& m_axis_ROCE, ap_uint<32> myIpAddress); +void ip_handler_top( + hls::stream >& s_axis_raw, + hls::stream >& m_axis_arp, + hls::stream >& m_axis_icmpv6, + hls::stream >& m_axis_ipv6udp, + hls::stream >& m_axis_icmp, + hls::stream >& m_axis_udp, + hls::stream >& m_axis_tcp, + hls::stream >& m_axis_roce, + ap_uint<32> myIpAddress); diff --git a/hls/ip_handler/newtcp.in b/hls/ip_handler/newtcp.in new file mode 100644 index 0000000..c784c93 --- /dev/null +++ b/hls/ip_handler/newtcp.in @@ -0,0 +1,51 @@ +0a 00 ab 89 67 45 23 01 ff 0 +00 45 00 08 e5 9d 02 35 ff 0 +01 40 00 40 00 00 54 00 ff 0 +01 01 0a 01 01 01 9d 36 ff 0 +b4 63 b7 c0 00 00 01 01 ff 0 +00 00 51 cd 55 b8 01 00 ff 0 +00 00 00 0d 18 8a 00 00 ff 0 +15 14 13 12 11 10 00 00 ff 0 +1d 1c 1b 1a 19 18 17 16 ff 0 +25 24 23 22 21 20 1f 1e ff 0 +2d 2c 2b 2a 29 28 27 26 ff 0 +35 34 33 32 31 30 2f 2e ff 0 +00 00 00 00 00 00 37 36 03 1 +0a 00 ab 89 67 45 23 01 ff 0 +00 45 00 08 e5 9d 02 35 ff 0 +01 40 00 40 00 00 54 00 ff 0 +01 01 0a 01 01 01 9d 36 ff 0 +b4 63 b7 c0 00 00 01 01 ff 0 +00 00 51 cd 55 b8 01 00 ff 0 +00 00 00 0d 18 8a 00 00 ff 0 +15 14 13 12 11 10 00 00 ff 0 +1d 1c 1b 1a 19 18 17 16 ff 0 +25 24 23 22 21 20 1f 1e ff 0 +2d 2c 2b 2a 29 28 27 26 ff 0 +35 34 33 32 31 30 2f 2e ff 0 +00 00 00 00 00 00 37 36 03 1 +0a 00 69 9a 45 dd 60 00 ff 0 +00 45 00 08 e5 9d 02 35 ff 0 +06 40 00 00 00 00 37 00 ff 0 +01 01 01 01 01 01 b5 76 ff 0 +23 56 2c df cd 2b 0a 01 ff 0 +10 50 d2 b8 71 9b b1 01 ff 0 +48 0e 00 00 de 95 ff ff ff 0 +6c 65 4d 20 6f 6c 6c 65 ff 0 +00 00 00 2e 72 65 78 65 1f 1 +0a 00 69 9a 45 dd 60 00 ff 0 +00 45 00 08 e5 9d 02 35 ff 0 +06 40 00 00 00 00 28 00 ff 0 +01 01 01 01 01 01 c4 76 ff 0 +23 56 2c df cd 2b 0a 01 ff 0 +11 50 d3 b8 71 9b c0 01 ff 0 +00 00 00 00 a5 f4 fe ff 3f 1 +0a 00 69 9a 45 dd 60 00 ff 0 +00 45 00 08 e5 9d 02 35 ff 0 +06 40 00 00 00 00 37 00 ff 0 +01 01 01 01 01 01 b5 76 ff 0 +23 56 c1 ab cd 2b 0a 01 ff 0 +10 50 a9 d8 87 4b b1 01 ff 0 +48 0e 00 00 5c f9 ff ff ff 0 +6c 65 4d 20 6f 6c 6c 65 ff 0 +00 00 00 2e 72 65 78 65 1f 1 From d425d123502bc12552c97245fd6bd3d1462f2f57 Mon Sep 17 00:00:00 2001 From: Viktor Khristenko Date: Wed, 4 Mar 2020 17:42:22 +0100 Subject: [PATCH 2/3] update gitignore --- .gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitignore b/.gitignore index f5eb919..ee6ad52 100644 --- a/.gitignore +++ b/.gitignore @@ -52,3 +52,4 @@ synth/ *.csv *.out +iprepo/ From 4449fdcc55ad80a6f7745b724de6cdc61cf58319 Mon Sep 17 00:00:00 2001 From: Viktor Khristenko Date: Thu, 5 Mar 2020 09:09:27 +0100 Subject: [PATCH 3/3] fix create_project functionality --- CMakeLists.txt | 20 ++++++++++++++++++++ scripts/axi_infrastructure.tcl | 2 +- scripts/create_project.tcl.in | 16 ++++++++-------- scripts/create_vcu118_proj.tcl | 5 ++++- scripts/network_stack.tcl | 16 ++++++++-------- scripts/network_ultraplus.tcl | 2 +- 6 files changed, 42 insertions(+), 19 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 006d4f7..4f1b688 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -84,3 +84,23 @@ add_subdirectory(hls/hash_table) if (NOT hasParent) add_subdirectory(hls/ethernet_frame_padding) endif() + +if (NOT hasParent) + + # Find Xilinx Vivado + find_package(Vivado REQUIRED) + if (NOT VIVADO_FOUND) + message(FATAL_ERROR "Vivado not found.") + endif() + + configure_file(${CMAKE_SOURCE_DIR}/scripts/create_project.tcl.in create_project.tcl) + + #set (PROJECT_DEPENDS + # ${CMAKE_SOURCE_DIR}/rtl/common/network_stack.v + # ${CMAKE_SOURCE_DIR}/projects/create_project.tcl.in + # ${CMAKE_SOURCE_DIR}/projects/network_stack.tcl) + + add_custom_target(project + COMMAND ${VIVADO_BINARY} -mode batch -source create_project.tcl) + #DEPENDS ${PROJECT_DEPENDS}) +endif() diff --git a/scripts/axi_infrastructure.tcl b/scripts/axi_infrastructure.tcl index 0182d1e..1f8466a 100755 --- a/scripts/axi_infrastructure.tcl +++ b/scripts/axi_infrastructure.tcl @@ -2,7 +2,7 @@ #FIFOs -create_ip -name axis_data_fifo -vendor xilinx.com -library ip -version 1.1 -module_name axis_data_fifo_64_cc -dir $device_ip_dir +create_ip -name axis_data_fifo -vendor xilinx.com -library ip -version * -module_name axis_data_fifo_64_cc -dir $device_ip_dir set_property -dict [list CONFIG.TDATA_NUM_BYTES {8} CONFIG.IS_ACLK_ASYNC {1} CONFIG.HAS_TKEEP {1} CONFIG.HAS_TLAST {1} CONFIG.SYNCHRONIZATION_STAGES {3} CONFIG.Component_Name {axis_data_fifo_64_cc}] [get_ips axis_data_fifo_64_cc] generate_target {instantiation_template} [get_files $device_ip_dir/axis_data_fifo_64_cc/axis_data_fifo_64_cc.xci] update_compile_order -fileset sources_1 diff --git a/scripts/create_project.tcl.in b/scripts/create_project.tcl.in index a2ab506..e8b800a 100755 --- a/scripts/create_project.tcl.in +++ b/scripts/create_project.tcl.in @@ -1,7 +1,7 @@ set proj_name "network_stack_example_prj" set root_dir [pwd] set proj_dir $root_dir/$proj_name -set src_dir $root_dir/../rtl +set src_dir $root_dir/../hdl set ip_dir $root_dir/../ip set ip_repo $root_dir/../iprepo set constraints_dir $root_dir/../constraints @@ -14,7 +14,7 @@ if { [file isdirectory $ip_repo] } { exit 1 } # Create project -create_project $proj_name $proj_dir +create_project -force $proj_name $proj_dir # Set project properties set obj [get_projects $proj_name] @@ -42,19 +42,19 @@ set device_ip_dir $ip_dir/${DEVICE_NAME} #Create IPs #Network interface -source ${CMAKE_SOURCE_DIR}/projects/network_${FPGA_FAMILY}.tcl +source ${CMAKE_SOURCE_DIR}/scripts/network_${FPGA_FAMILY}.tcl #AXI Infrastructure: FIFOs, Register slices, Interconnect -source ${CMAKE_SOURCE_DIR}/projects/axi_infrastructure.tcl +source ${CMAKE_SOURCE_DIR}/scripts/axi_infrastructure.tcl #Network stack -source ${CMAKE_SOURCE_DIR}/projects/network_stack.tcl +source ${CMAKE_SOURCE_DIR}/scripts/network_stack.tcl #VIOs -source ${CMAKE_SOURCE_DIR}/projects/common.tcl +source ${CMAKE_SOURCE_DIR}/scripts/common.tcl #Memory interface -source ${CMAKE_SOURCE_DIR}/projects/dram_${FPGA_FAMILY}.tcl +source ${CMAKE_SOURCE_DIR}/scripts/dram_${FPGA_FAMILY}.tcl -start_gui +#start_gui diff --git a/scripts/create_vcu118_proj.tcl b/scripts/create_vcu118_proj.tcl index e6cabe2..f3db813 100755 --- a/scripts/create_vcu118_proj.tcl +++ b/scripts/create_vcu118_proj.tcl @@ -1,11 +1,14 @@ set proj_name "tcp_ip_vcu118" set root_dir [pwd] set proj_dir $root_dir/$proj_name -set src_dir $root_dir/../rtl +set src_dir $root_dir/../hdl set ip_dir $root_dir/../ip set ip_repo $root_dir/../iprepo set constraints_dir $root_dir/../constraints +puts "root_dir = $root_dir" +puts "ip_repo = $ip_repo" + #Check if iprepo is available if { [file isdirectory $ip_repo] } { set lib_dir "$ip_repo" diff --git a/scripts/network_stack.tcl b/scripts/network_stack.tcl index ad7b57d..ab04ebd 100755 --- a/scripts/network_stack.tcl +++ b/scripts/network_stack.tcl @@ -36,15 +36,15 @@ set_property -dict [list CONFIG.Component_Name {axis_interconnect_merger_160} CO generate_target {instantiation_template} [get_files $device_ip_dir/axis_interconnect_merger_160/axis_interconnect_merger_160.xci] update_compile_order -fileset sources_1 -create_ip -name axis_interconnect -vendor xilinx.com -library ip -version 1.1 -module_name axis_interconnect_2to1 -dir $device_ip_dir -set_property -dict [list CONFIG.C_NUM_SI_SLOTS {2} CONFIG.SWITCH_TDATA_NUM_BYTES {8} CONFIG.HAS_TSTRB {false} CONFIG.HAS_TID {false} CONFIG.HAS_TDEST {false} CONFIG.SWITCH_PACKET_MODE {true} CONFIG.C_SWITCH_MAX_XFERS_PER_ARB {0} CONFIG.C_M00_AXIS_REG_CONFIG {1} CONFIG.C_S00_AXIS_REG_CONFIG {1} CONFIG.C_S01_AXIS_REG_CONFIG {1} CONFIG.C_SWITCH_NUM_CYCLES_TIMEOUT {0} CONFIG.M00_AXIS_TDATA_NUM_BYTES {8} CONFIG.S00_AXIS_TDATA_NUM_BYTES {8} CONFIG.S01_AXIS_TDATA_NUM_BYTES {8} CONFIG.M00_S01_CONNECTIVITY {true}] [get_ips axis_interconnect_2to1] -generate_target {instantiation_template} [get_files $device_ip_dir/axis_interconnect_2to1/axis_interconnect_2to1.xci] -update_compile_order -fileset sources_1 +#create_ip -name axis_interconnect -vendor xilinx.com -library ip -version 1.1 -module_name axis_interconnect_2to1 -dir $device_ip_dir +#set_property -dict [list CONFIG.C_NUM_SI_SLOTS {2} CONFIG.SWITCH_TDATA_NUM_BYTES {8} CONFIG.HAS_TSTRB {false} CONFIG.HAS_TID {false} CONFIG.HAS_TDEST {false} CONFIG.SWITCH_PACKET_MODE {true} CONFIG.C_SWITCH_MAX_XFERS_PER_ARB {0} CONFIG.C_M00_AXIS_REG_CONFIG {1} CONFIG.C_S00_AXIS_REG_CONFIG {1} CONFIG.C_S01_AXIS_REG_CONFIG {1} CONFIG.C_SWITCH_NUM_CYCLES_TIMEOUT {0} CONFIG.M00_AXIS_TDATA_NUM_BYTES {8} CONFIG.S00_AXIS_TDATA_NUM_BYTES {8} CONFIG.S01_AXIS_TDATA_NUM_BYTES {8} CONFIG.M00_S01_CONNECTIVITY {true}] [get_ips axis_interconnect_2to1] +#generate_target {instantiation_template} [get_files $device_ip_dir/axis_interconnect_2to1/axis_interconnect_2to1.xci] +#update_compile_order -fileset sources_1 -create_ip -name axis_interconnect -vendor xilinx.com -library ip -version 1.1 -module_name axis_interconnect_3to1 -dir $device_ip_dir -set_property -dict [list CONFIG.C_NUM_SI_SLOTS {3} CONFIG.SWITCH_TDATA_NUM_BYTES {8} CONFIG.HAS_TSTRB {false} CONFIG.HAS_TID {false} CONFIG.HAS_TDEST {false} CONFIG.SWITCH_PACKET_MODE {true} CONFIG.C_S00_AXIS_REG_CONFIG {1} CONFIG.C_S01_AXIS_REG_CONFIG {1} CONFIG.C_S02_AXIS_REG_CONFIG {1} CONFIG.C_SWITCH_MAX_XFERS_PER_ARB {0} CONFIG.C_SWITCH_NUM_CYCLES_TIMEOUT {0} CONFIG.M00_AXIS_TDATA_NUM_BYTES {8} CONFIG.S00_AXIS_TDATA_NUM_BYTES {8} CONFIG.S01_AXIS_TDATA_NUM_BYTES {8} CONFIG.S02_AXIS_TDATA_NUM_BYTES {8} CONFIG.M00_S01_CONNECTIVITY {true} CONFIG.M00_S02_CONNECTIVITY {true}] [get_ips axis_interconnect_3to1] -generate_target {instantiation_template} [get_files $device_ip_dir/axis_interconnect_3to1/axis_interconnect_3to1.xci] -update_compile_order -fileset sources_1 +#create_ip -name axis_interconnect -vendor xilinx.com -library ip -version 1.1 -module_name axis_interconnect_3to1 -dir $device_ip_dir +#set_property -dict [list CONFIG.C_NUM_SI_SLOTS {3} CONFIG.SWITCH_TDATA_NUM_BYTES {8} CONFIG.HAS_TSTRB {false} CONFIG.HAS_TID {false} CONFIG.HAS_TDEST {false} CONFIG.SWITCH_PACKET_MODE {true} CONFIG.C_S00_AXIS_REG_CONFIG {1} CONFIG.C_S01_AXIS_REG_CONFIG {1} CONFIG.C_S02_AXIS_REG_CONFIG {1} CONFIG.C_SWITCH_MAX_XFERS_PER_ARB {0} CONFIG.C_SWITCH_NUM_CYCLES_TIMEOUT {0} CONFIG.M00_AXIS_TDATA_NUM_BYTES {8} CONFIG.S00_AXIS_TDATA_NUM_BYTES {8} CONFIG.S01_AXIS_TDATA_NUM_BYTES {8} CONFIG.S02_AXIS_TDATA_NUM_BYTES {8} CONFIG.M00_S01_CONNECTIVITY {true} CONFIG.M00_S02_CONNECTIVITY {true}] [get_ips axis_interconnect_3to1] +#generate_target {instantiation_template} [get_files $device_ip_dir/axis_interconnect_3to1/axis_interconnect_3to1.xci] +#update_compile_order -fileset sources_1 create_ip -name axis_interconnect -vendor xilinx.com -library ip -version 1.1 -module_name axis_interconnect_4to1 -dir $device_ip_dir set_property -dict [list CONFIG.C_NUM_SI_SLOTS {4} CONFIG.SWITCH_TDATA_NUM_BYTES {8} CONFIG.HAS_TSTRB {false} CONFIG.HAS_TID {false} CONFIG.HAS_TDEST {false} CONFIG.SWITCH_PACKET_MODE {true} CONFIG.C_SWITCH_MAX_XFERS_PER_ARB {0} CONFIG.C_M00_AXIS_REG_CONFIG {1} CONFIG.C_S00_AXIS_REG_CONFIG {1} CONFIG.C_S01_AXIS_REG_CONFIG {1} CONFIG.C_S02_AXIS_REG_CONFIG {1} CONFIG.C_S03_AXIS_REG_CONFIG {1} CONFIG.C_SWITCH_NUM_CYCLES_TIMEOUT {0} CONFIG.M00_AXIS_TDATA_NUM_BYTES {8} CONFIG.S00_AXIS_TDATA_NUM_BYTES {8} CONFIG.S01_AXIS_TDATA_NUM_BYTES {8} CONFIG.S02_AXIS_TDATA_NUM_BYTES {8} CONFIG.S03_AXIS_TDATA_NUM_BYTES {8} CONFIG.M00_S01_CONNECTIVITY {true} CONFIG.M00_S02_CONNECTIVITY {true} CONFIG.M00_S03_CONNECTIVITY {true}] [get_ips axis_interconnect_4to1] diff --git a/scripts/network_ultraplus.tcl b/scripts/network_ultraplus.tcl index 126fe6f..2dfba16 100755 --- a/scripts/network_ultraplus.tcl +++ b/scripts/network_ultraplus.tcl @@ -1,6 +1,6 @@ #Network interface -create_ip -name xxv_ethernet -vendor xilinx.com -library ip -version 2.4 -module_name ethernet_10g_ip -dir $device_ip_dir +create_ip -name xxv_ethernet -vendor xilinx.com -library ip -version * -module_name ethernet_10g_ip -dir $device_ip_dir set_property -dict [list CONFIG.LINE_RATE {10} CONFIG.NUM_OF_CORES {1} CONFIG.INCLUDE_AXI4_INTERFACE {0} CONFIG.GT_REF_CLK_FREQ {161.1328125} CONFIG.GT_DRP_CLK {125} CONFIG.GT_GROUP_SELECT {Quad_X1Y12} CONFIG.LANE1_GT_LOC {X1Y48} CONFIG.ENABLE_PIPELINE_REG {1} CONFIG.Component_Name {ethernet_10g_ip}] [get_ips ethernet_10g_ip] generate_target {instantiation_template} [get_files $device_ip_dir/ethernet_10g_ip/ethernet_10g_ip.xci] update_compile_order -fileset sources_1