CodeGen_ARM tries to narrow a vector reduce of uint8 to uint1 to use the widening intrinsic.

[mcourteaux]

CodeGen for ARM for this expression:

(int8x5)vector_reduce_add((int8x10)vector_reduce_max(x30((int8)1)))

Fails with:

Internal error at src/IR.cpp:971
Condition failed: op == VectorReduce::And || op == VectorReduce::Or
Error: The only legal operators for VectorReduce on a Boolvector are VectorReduce::And and VectorReduce::Or

Error is produced when doing this:

Halide/src/CodeGen_ARM.cpp

Lines 2269 to 2277 in 6694e5d

	if (op->op == VectorReduce::Add && factor == 2) {
	Type narrow_type = op->type.narrow().with_lanes(op->value.type().lanes());
	Expr narrow = lossless_cast(narrow_type, op->value);
	if (!narrow.defined() && op->type.is_int()) {
	// We can also safely accumulate from a uint into a
	// wider int, because the addition uses at most one
	// extra bit.
	narrow = lossless_cast(narrow_type.with_code(Type::UInt), op->value);
	}

Because the vector reduce is within a vector reduce, the narrowing logic tries to produce an int1 vector_reduce with the max operator, which it doesn't like.

(Assignees based on git-blame of the surrounding code)