Merge pull request #1938 from Gelbpunkt/32-bit-pci-bars

32-bit PCI bar support

Author: mkroening

src/arch/aarch64/kernel/pci.rs

@@ -240,7 +240,7 @@ pub fn init() {
 			flags,
 		);
 
-		let (mut io_start, mem32_start, mut mem64_start) = detect_pci_regions(pci_node);
+		let (mut io_start, mut mem32_start, mut mem64_start) = detect_pci_regions(pci_node);
 
 		debug!("IO address space starts at{io_start:#X}");
 		debug!("Memory32 address space starts at {mem32_start:#X}");
@@ -267,7 +267,8 @@ pub fn init() {
 
 					// Initializes BARs
 					let mut cmd = CommandRegister::empty();
-					for i in 0..MAX_BARS {
+					let mut range_iter = 0..MAX_BARS;
+					while let Some(i) = range_iter.next() {
 						if let Some(bar) = dev.get_bar(i.try_into().unwrap()) {
 							match bar {
 								Bar::Io { .. } => {
@@ -281,11 +282,22 @@ pub fn init() {
 									cmd |= CommandRegister::IO_ENABLE
 										| CommandRegister::BUS_MASTER_ENABLE;
 								}
-								Bar::Memory32 { .. } => {
-									// Currently, we ignore 32 bit memory bars
-									// dev.set_bar(i.try_into().unwrap(), Bar::Memory32 { address: mem32_start.try_into().unwrap(), size,  prefetchable });
-									// mem32_start += u64::from(size);
-									// cmd |= CommandRegister::MEMORY_ENABLE | CommandRegister::BUS_MASTER_ENABLE;
+								Bar::Memory32 {
+									address: _,
+									size,
+									prefetchable,
+								} => {
+									dev.set_bar(
+										i.try_into().unwrap(),
+										Bar::Memory32 {
+											address: mem32_start.try_into().unwrap(),
+											size,
+											prefetchable,
+										},
+									);
+									mem32_start += u64::from(size);
+									cmd |= CommandRegister::MEMORY_ENABLE
+										| CommandRegister::BUS_MASTER_ENABLE;
 								}
 								Bar::Memory64 {
 									address: _,
@@ -303,6 +315,7 @@ pub fn init() {
 									mem64_start += size;
 									cmd |= CommandRegister::MEMORY_ENABLE
 										| CommandRegister::BUS_MASTER_ENABLE;
+									range_iter.next(); // Skip 32-bit bar that is part of the 64-bit bar
 								}
 							}
 						}

src/drivers/pci.rs

@@ -137,7 +137,7 @@ impl<T: ConfigRegionAccess> PciDevice<T> {
 	/// no_cache determines if we set the `Cache Disable` flag in the page-table-entry.
 	/// Returns (virtual-pointer, size) if successful, else None (if bar non-existent or IOSpace)
 	pub fn memory_map_bar(&self, index: u8, no_cache: bool) -> Option<(VirtAddr, usize)> {
-		let (address, size, prefetchable, width) = match self.get_bar(index) {
+		let (address, size, prefetchable, _width) = match self.get_bar(index) {
 			Some(Bar::Io { .. }) => {
 				warn!("Cannot map IOBar!");
 				return None;
@@ -168,10 +168,6 @@ impl<T: ConfigRegionAccess> PciDevice<T> {
 
 		debug!("Mapping bar {index} at {address:#x} with length {size:#x}");
 
-		if width != 64 {
-			warn!("Currently only mapping of 64 bit bars is supported!");
-			return None;
-		}
 		if !prefetchable {
 			warn!("Currently only mapping of prefetchable bars is supported!");
 		}