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trbauer
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Internal Feature
Change-Id: Ieae86dca388fe8b07e77a40caeb2d4034e05c270
1 parent 0403fd9 commit 12cc781

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8 files changed

+268
-57
lines changed

8 files changed

+268
-57
lines changed

‎visa/BinaryEncodingIGA.cpp

Lines changed: 11 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -870,24 +870,25 @@ SendDescArg BinaryEncodingIGA::getIGASendDescArg(G4_INST* sendInst) const
870870

871871
iga::SendDescArg BinaryEncodingIGA::getIGASendExDescArg(G4_INST* sendInst) const
872872
{
873-
iga::SendDescArg desc;
874-
desc.init();
873+
iga::SendDescArg exDescArg{ };
874+
875875
assert(sendInst->isSend() && "expect send inst");
876876
if (sendInst->isSplitSend())
877877
{
878878
G4_Operand* exDesc = sendInst->getSrc(3);
879879
if (exDesc->isImm())
880880
{
881-
desc.type = SendDescArg::IMM;
881+
exDescArg.type = SendDescArg::IMM;
882882
uint32_t tVal = (uint32_t)exDesc->asImm()->getImm();
883-
desc.imm = tVal;
883+
exDescArg.imm = tVal;
884884
}
885885
else
886886
{
887-
desc.type = SendDescArg::REG32A;
888-
desc.reg.regNum = 0; // must be a0
887+
exDescArg.type = SendDescArg::REG32A;
888+
exDescArg.reg.regNum = 0; // must be a0
889889
bool valid = false;
890-
desc.reg.subRegNum = (uint8_t) exDesc->asSrcRegRegion()->ExSubRegNum(valid);
890+
exDescArg.reg.subRegNum =
891+
(uint8_t)exDesc->asSrcRegRegion()->ExSubRegNum(valid);
891892
assert(valid && "invalid subreg");
892893
}
893894
}
@@ -896,13 +897,13 @@ iga::SendDescArg BinaryEncodingIGA::getIGASendExDescArg(G4_INST* sendInst) const
896897
// exDesc is stored in SendMsgDesc and must be IMM
897898
G4_SendMsgDescriptor* sendDesc = sendInst->getMsgDesc();
898899
assert(sendDesc != nullptr && "null msg desc");
899-
desc.type = SendDescArg::IMM;
900+
exDescArg.type = SendDescArg::IMM;
900901
uint32_t tVal = sendDesc->getExtendedDesc();
901902

902-
desc.imm = tVal;
903+
exDescArg.imm = tVal;
903904
}
904905

905-
return desc;
906+
return exDescArg;
906907
}
907908

908909
void *BinaryEncodingIGA::EmitBinary(uint32_t& binarySize)

‎visa/BuildIR.h

Lines changed: 38 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2473,6 +2473,44 @@ class IR_Builder {
24732473
unsigned batchExSize, bool splitSendEnabled,
24742474
payloadSource sources[], unsigned len);
24752475

2476+
// Coalesce multiple payloads into a single region. Pads each region with
2477+
// an optional alignment argument (e.g. a GRF size). The source region
2478+
// sizes are determined by source dimension, so use an alias if you are
2479+
// using a subregion. All copies are made under no mask semantics using
2480+
// the maximal SIMD width for the current device.
2481+
//
2482+
// A second alignment option allows a caller to align the full payload
2483+
// to some total.
2484+
//
2485+
// If all parameters are nullptr or the null register, we return the null
2486+
// register.
2487+
//
2488+
// Some examples:
2489+
//
2490+
// 1. coalescePayloads(GRF_SIZE,GRF_SIZE,...);
2491+
// Coalesces each source into a single region. Each source is padded
2492+
// out to a full GRF, and the sum total result is also padded out to
2493+
// a full GRF.
2494+
//
2495+
// 2. coalescePayloads(1,GRF_SIZE,...);
2496+
// Coalesces each source into a single region packing each source
2497+
// together, but padding the result. E.g. one could copy a QW and then
2498+
// a DW and pad the result out to a GRF.
2499+
//
2500+
G4_SrcRegRegion *coalescePayload(
2501+
unsigned alignSourcesTo,
2502+
unsigned alignPayloadTo,
2503+
std::initializer_list<G4_SrcRegRegion *> srcs);
2504+
2505+
// struct PayloadElem {
2506+
// enum PayloadKind {REG,IMM};
2507+
// union {
2508+
// G4_SrcRegRegion *reg;
2509+
// G4_Imm *imm;
2510+
// }
2511+
// size_t alignTo;
2512+
// };
2513+
24762514
#define FIX_OWORD_SEND_EXEC_SIZE(BLOCK_SIZE)(((BLOCK_SIZE) > 2)? 16: (BLOCK_SIZE*4))
24772515

24782516
// return either 253 or 255 for A64 messages, depending on whether we want I/A coherency or not

‎visa/CISA.l

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -107,6 +107,7 @@ static int pendingBracket;
107107
")" {TRACE("\n** RPAREN "); return RPAREN;}
108108
"{" {TRACE("\n** LBRACE "); return LBRACE;}
109109
"}" {TRACE("\n** RBRACE "); return RBRACE;}
110+
"," {TRACE("\n** COMMA "); return COMMA;}
110111

111112
".version" {TRACE("\n** VERSION "); return DIRECTIVE_VERSION;}
112113
".entry" {TRACE("\n** ENTRY "); return DIRECTIVE_ENTRY;}

‎visa/CISA.y

Lines changed: 15 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -306,6 +306,7 @@ VISA_RawOpnd* rawOperandArray[16];
306306
%token <string> RPAREN /* ) */
307307
%token <string> LBRACE /* { */
308308
%token <string> RBRACE /* } */
309+
%token <string> COMMA /* , */
309310
%token <string> IND_LEFT_BRACKET /* r[ */
310311
%token <string> PLUS /* + */
311312
%token <string> MINUS /* - */
@@ -815,7 +816,7 @@ AliasInfo : /* empty */
815816
$$.aliasname = NULL;
816817
$$.offset = 0;
817818
}
818-
| ALIAS '<'VAR','Exp'>'
819+
| ALIAS '<' VAR COMMA Exp '>'
819820
{
820821
$$.aliasname = $3;
821822
$$.offset = (int)$5;
@@ -1278,7 +1279,7 @@ SwitchLabels: /* empty */
12781279
{
12791280
$$ = 0;
12801281
}
1281-
| ',' SwitchLabels
1282+
| COMMA SwitchLabels
12821283
{
12831284
$$ = $2;
12841285
}
@@ -1580,14 +1581,14 @@ VecSrcOpndSimple : VAR TwoDimOffset
15801581
$$.cisa_gen_opnd = pCisaBuilder->CISA_create_gen_src_operand($1, 1, 1, 0, $2.row, $2.elem, MODIFIER_NONE, CISAlineno);
15811582
};
15821583

1583-
// 1 2 3 4 5
1584-
VMEOpndIME : LPAREN NUMBER ',' NUMBER RPAREN
1584+
// 1 2 3 4 5
1585+
VMEOpndIME : LPAREN NUMBER COMMA NUMBER RPAREN
15851586
{
15861587
$$.streamMode = (unsigned char)$2;
15871588
$$.searchCtrl = (unsigned char)$4;
15881589
};
1589-
// 1 2 3 4 5 6 7
1590-
VMEOpndFBR : LPAREN VecSrcOperand_G_I_IMM ',' VecSrcOperand_G_I_IMM ',' VecSrcOperand_G_I_IMM RPAREN
1590+
// 1 2 3 4 5 6 7
1591+
VMEOpndFBR : LPAREN VecSrcOperand_G_I_IMM COMMA VecSrcOperand_G_I_IMM COMMA VecSrcOperand_G_I_IMM RPAREN
15911592
{
15921593
//$$.fbrMbMode = $2.opnd;
15931594
//$$.fbrSubMbShape = $4.opnd;
@@ -1764,7 +1765,7 @@ SrcRegion : /* empty */
17641765
$$.h_stride = 0;
17651766
//$$.rgn = NULL;
17661767
}
1767-
| '<' Exp ';' Exp ',' Exp '>' /* <VertStride;Width,HorzStride> */
1768+
| '<' Exp ';' Exp COMMA Exp '>' /* <VertStride;Width,HorzStride> */
17681769
{
17691770
MUST_HOLD(($2 == 0 || $2 == 1 || $2 == 2 || $2 == 4 || $2 == 8 || $2 == 16 || $2 == 32),
17701771
"VertStride must be 0, 1, 2, 4, 8, 16, or 32");
@@ -1789,7 +1790,7 @@ Region : /* empty */
17891790
$$.h_stride = -1;
17901791
//$$.rgn = NULL;
17911792
}
1792-
| '<' Exp ';' Exp ',' Exp '>' /* <VertStride;Width,HorzStride> */
1793+
| '<' Exp ';' Exp COMMA Exp '>' /* <VertStride;Width,HorzStride> */
17931794
{
17941795
MUST_HOLD(($2 == 0 || $2 == 1 || $2 == 2 || $2 == 4 || $2 == 8 || $2 == 16 || $2 == 32),
17951796
"VertStride must be 0, 1, 2, 4, 8, 16, or 32");
@@ -1803,7 +1804,7 @@ Region : /* empty */
18031804
//$$.rgn = pBuilder->rgnpool.createRegion($2, $4, $6);
18041805
};
18051806

1806-
RegionWH : '<' Exp ',' Exp '>' /* <Width,HorzStride> */
1807+
RegionWH : '<' Exp COMMA Exp '>' /* <Width,HorzStride> */
18071808
{
18081809
MUST_HOLD(($2 == 0 || $2 == 1 || $2 == 2 || $2 == 4 || $2 == 8 || $2 == 16),
18091810
"Width must be 0, 1, 2, 4, 8 or 16");
@@ -1846,13 +1847,13 @@ AddrParam : AddrVar ImmAddrOffset
18461847

18471848
ImmAddrOffset : /* empty */
18481849
{$$ = 0;} /* default to 0 */
1849-
| ',' Exp /* need to chech whether the number is between -512 ... 511 */
1850+
| COMMA Exp /* need to chech whether the number is between -512 ... 511 */
18501851
{
18511852
MUST_HOLD(($2 <= 511 && $2 >= -512),"imm addr offset must be -512 .. 511");
18521853
$$ = $2;
18531854
};
18541855

1855-
TwoDimOffset : LPAREN Exp ',' Exp RPAREN
1856+
TwoDimOffset : LPAREN Exp COMMA Exp RPAREN
18561857
{
18571858
$$.row = (int)$2;
18581859
$$.elem = (int)$4;
@@ -1888,7 +1889,7 @@ AddrVar : VAR
18881889
$$.row = (int)$6;
18891890
$$.elem = (int)$3;
18901891
}
1891-
| VAR LPAREN Exp ',' Exp RPAREN
1892+
| VAR LPAREN Exp COMMA Exp RPAREN
18921893
{
18931894
TRACE("\n** Address operand");
18941895
$$.cisa_decl = pCisaBuilder->CISA_find_decl($1);
@@ -1954,7 +1955,7 @@ ExecSize : /* empty */
19541955
$$.emask = vISA_EMASK_M1;
19551956
$$.exec_size = (int)$2;
19561957
};
1957-
| LPAREN EMASK ',' NUMBER RPAREN
1958+
| LPAREN EMASK COMMA NUMBER RPAREN
19581959
{
19591960
TRACE("\n** Execution Size ");
19601961
MUST_HOLD(($4 == 0 || $4 == 1 || $4 == 2 || $4 == 4 || $4 == 8 || $4 == 16 || $4 == 32),
@@ -2121,7 +2122,7 @@ VISA_Type variable_declaration_and_type_check(char *var, Common_ISA_Var_Class ty
21212122
}
21222123
*/
21232124

2124-
void yyerror (char const *s)
2125+
void yyerror(char const *s)
21252126
{
21262127

21272128
int yytype = YYTRANSLATE (yychar);

‎visa/Common_ISA_framework.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -72,7 +72,7 @@ int CisaInst::createCisaInstruction(
7272
}
7373
}
7474

75-
// TODO: move the FIXME below above this if statment, and
75+
// TODO: move the FIXME below above this if statment and
7676
// int implicitOperands = 0;
7777
// for (...) // parent op descriptors
7878
// if (type == EXEC_SIZE || type == PRED)
@@ -84,6 +84,7 @@ int CisaInst::createCisaInstruction(
8484
// TODO: rename descOpndCount to descOpndsToEncodeCount
8585
//
8686
// compare (descOpndCount != explicitOpnds + implicitOperands)
87+
// mismatch assert
8788
if (opcode != ISA_FCALL)
8889
{
8990
// != doens't work here because predication and exec size are treated

‎visa/Gen4_IR.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -4738,7 +4738,7 @@ void G4_DstRegRegion::setDstBitVec( uint8_t exec_size )
47384738
{
47394739
footprint1 |= bit_seq << (eltOffset - 64);
47404740
}
4741-
else
4741+
else
47424742
{
47434743
footprint0 |= bit_seq << eltOffset;
47444744
}
@@ -5550,8 +5550,8 @@ G4_SubReg_Align G4_Declare::getSubRegAlign() const
55505550
return regVar->getSubRegAlignment();
55515551
}
55525552

5553-
void
5554-
G4_Declare::emit(std::ostream &output, bool isDumpDot, bool isSymbolReg)
5553+
void G4_Declare::emit(
5554+
std::ostream &output, bool isDumpDot, bool isSymbolReg) const
55555555
{
55565556

55575557
//
@@ -6398,7 +6398,7 @@ void G4_SrcRegRegion::setSrcBitVec(uint8_t exec_size)
63986398

63996399
footPrint0 = totalBytes < 64 ? (1ULL << totalBytes) - 1 : ULLONG_MAX;
64006400
if (totalBytes > 64)
6401-
{
6401+
{
64026402
footPrint1 = totalBytes == 128 ? ULLONG_MAX : (1ULL << (totalBytes - 64)) - 1;
64036403
}
64046404
}
@@ -6868,7 +6868,7 @@ void G4_Operand::updateFootPrint(BitSet& footprint, bool isSet)
68686868
unsigned lb = getLeftBound();
68696869
unsigned rb = getRightBound();
68706870
const bool doFastPath = true; // for debugging
6871-
6871+
68726872
if (doFastPath && lb % N == 0 && (rb + 1) % N == 0)
68736873
{
68746874
// lb is 32-byte aligned, set one dword at a time

‎visa/Gen4_IR.hpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1847,7 +1847,7 @@ class G4_Declare
18471847
}
18481848

18491849
G4_Type getElemType() const {return elemType;}
1850-
uint16_t getElemSize() const { return static_cast<uint16_t>(G4_Type_Table[elemType].byteSize); }
1850+
uint16_t getElemSize() const {return static_cast<uint16_t>(G4_Type_Table[elemType].byteSize);}
18511851
const G4_RegVar *getRegVar() const {return regVar;}
18521852
G4_RegVar *getRegVar() {return regVar;}
18531853

@@ -1906,7 +1906,7 @@ class G4_Declare
19061906
}
19071907
}
19081908

1909-
void emit(std::ostream& output, bool isDumpDot, bool isSymbolReg);
1909+
void emit(std::ostream& output, bool isDumpDot, bool isSymbolReg) const;
19101910

19111911
void prepareForRealloc(G4_Kernel*);
19121912
};

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