Spill/fill improvement

bcheng0127 · sys_zuul · commit 6dd3bde8f93e · 2019-08-22T01:22:43.000-07:00
Change-Id: Ibc6189f26eeaaef1a35666a9ca98a0c3ae5c9bf0
diff --git a/visa/BuildIR.h b/visa/BuildIR.h
@@ -828,6 +828,7 @@ class IR_Builder {
             builtinR0 = R0CopyDcl;
         }
 
+
         builtinA0 = createDeclareNoLookup(
             "BuiltinA0",
             G4_ADDRESS,
diff --git a/visa/GraphColor.cpp b/visa/GraphColor.cpp
@@ -8822,7 +8822,7 @@ int GlobalRA::coloringRegAlloc()
                 coloring.dumpRegisterPressure();
             }
 
-            unsigned spillRegSize = iterationNo;
+            unsigned spillRegSize = 0;
             unsigned indrSpillRegSize = 0;
             bool isColoringGood = coloring.regAlloc(doBankConflictReduction, highInternalConflict, reserveSpillReg, spillRegSize, indrSpillRegSize, &rpe);
             if (isColoringGood == false)

Original file line number	Diff line number	Diff line change
`@@ -828,6 +828,7 @@ class IR_Builder {`
`828`	`828`	`builtinR0 = R0CopyDcl;`
`829`	`829`	`}`
`830`	`830`
	`831`	`+`
`831`	`832`	`builtinA0 = createDeclareNoLookup(`
`832`	`833`	`"BuiltinA0",`
`833`	`834`	`G4_ADDRESS,`
Original file line number	Diff line number	Diff line change
`@@ -8822,7 +8822,7 @@ int GlobalRA::coloringRegAlloc()`
`8822`	`8822`	`coloring.dumpRegisterPressure();`
`8823`	`8823`	`}`
`8824`	`8824`
`8825`		`- unsigned spillRegSize = iterationNo;`
	`8825`	`+ unsigned spillRegSize = 0;`
`8826`	`8826`	`unsigned indrSpillRegSize = 0;`
`8827`	`8827`	`bool isColoringGood = coloring.regAlloc(doBankConflictReduction, highInternalConflict, reserveSpillReg, spillRegSize, indrSpillRegSize, &rpe);`
`8828`	`8828`	`if (isColoringGood == false)`