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DianaChen
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IGA: Refactor encoder/decoder
Change-Id: I172cad4a0f65eecdf49a14fed8267d72b13cb0b9
1 parent e1ecdea commit 85a4012

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12 files changed

+135
-64
lines changed

12 files changed

+135
-64
lines changed

‎visa/iga/GEDLibrary/GED_external/Source/common/version.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -24,4 +24,4 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
2424
2525
======================= end_copyright_notice ==================================*/
2626

27-
const char* gedVersion = "0.25 (c9497486)";
27+
const char* gedVersion = "0.26 (eccab5d0)";

‎visa/iga/IGALibrary/Backend/GED/Decoder.cpp

Lines changed: 23 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -491,6 +491,7 @@ void DecoderBase::decodeBasicDestinationAlign16(Instruction *inst)
491491
}
492492

493493
GED_DECODE_RAW(int32_t, addrImm, DstAddrImm);
494+
494495
GED_DECODE_RAW(uint32_t, subRegNum, DstAddrSubRegNum);
495496
RegRef a0 = {0, (uint8_t)subRegNum};
496497
inst->setInidirectDestination(
@@ -723,7 +724,7 @@ void DecoderBase::decodeTernaryDestinationAlign16(Instruction *inst)
723724

724725
GED_DECODE_RAW(uint32_t, subRegNumBytes, DstSubRegNum);
725726
uint8_t subRegNumber = type == Type::INVALID ?
726-
0 : BytesOffsetToSubReg((uint8_t)subRegNumBytes, regName, type);
727+
0 : binNumToSubRegNum((uint8_t)subRegNumBytes, regName, type, true);
727728
regRef.subRegNum = (uint8_t)(subRegNumber + subregOffAlign16Elems);
728729
inst->setDirectDestination(
729730
dstMod,
@@ -779,7 +780,7 @@ void DecoderBase::decodeTernarySourceAlign16(Instruction *inst)
779780
type);
780781
} else {
781782
int subReg = type == Type::INVALID ?
782-
0 : BytesOffsetToSubReg(decodeSrcSubRegNum<S>(), RegName::GRF_R, type);
783+
0 : binNumToSubRegNum(decodeSrcSubRegNum<S>(), RegName::GRF_R, type, true);
783784
RegRef reg = {
784785
(uint8_t)regNum,
785786
(uint8_t)subReg
@@ -1333,11 +1334,14 @@ Predication DecoderBase::decodePredication()
13331334
Predication pred = {PredCtrl::NONE, false};
13341335
GED_DECODE_RAW(GED_PRED_CTRL, pc, PredCtrl);
13351336
pred.function = GEDToIGATranslation::translate(pc);
1336-
GED_DECODE_RAW(GED_PRED_INV, pi, PredInv);
1337-
pred.inverse = (pi == GED_PRED_INV_Invert);
13381337
return pred;
13391338
}
13401339

1340+
void DecoderBase::decodePredInv(Predication& pred)
1341+
{
1342+
GED_DECODE_RAW(GED_PRED_INV, pi, PredInv);
1343+
pred.inverse = (pi == GED_PRED_INV_Invert);
1344+
}
13411345

13421346
MaskCtrl DecoderBase::decodeMaskCtrl()
13431347
{
@@ -1357,11 +1361,14 @@ FlagRegInfo DecoderBase::decodeFlagRegInfo(bool imm64Src0Overlaps) {
13571361
if (m_opSpec->supportsFlagModifier() && !imm64Src0Overlaps) {
13581362
GED_DECODE_RAW(GED_COND_MODIFIER, condMod, CondModifier);
13591363
fri.modifier = GEDToIGATranslation::translate(condMod);
1360-
} else if (m_opSpec-> isMathSubFunc() && m_opSpec->isMacro()) {
1364+
} else if (m_opSpec->isMathSubFunc() && m_opSpec->isMacro()) {
13611365
// math.inv and math.rsqrtm both implicitly support EO
13621366
fri.modifier = FlagModifier::EO;
13631367
}
13641368

1369+
if (m_opSpec->supportsPredication())
1370+
decodePredInv(fri.pred);
1371+
13651372
if (fri.pred.function != PredCtrl::NONE ||
13661373
fri.modifier != FlagModifier::NONE)
13671374
{
@@ -1487,7 +1494,8 @@ void DecoderBase::decodeDstDirSubRegNum(DirRegOpInfo& dri)
14871494

14881495
GED_DECODE_RAW(uint32_t, subRegNum, DstSubRegNum);
14891496
dri.regRef.subRegNum =
1490-
BytesOffsetToSubReg((uint8_t)subRegNum, dri.regName, scalingType);
1497+
binNumToSubRegNum((uint8_t)subRegNum, dri.regName, scalingType,
1498+
m_opSpec->isBranching() || m_opSpec->isTernary());
14911499
}
14921500
}
14931501

@@ -1625,11 +1633,12 @@ void DecoderBase::decodeSourceBasicAlign1(Instruction *inst, SourceIndex toSrcIx
16251633
}
16261634
} else if (addrMode == GED_ADDR_MODE_Indirect) {
16271635
RegRef a0 = {0, (uint8_t)decodeSrcAddrSubRegNum<S>()};
1636+
int16_t addr_imm = decodeSrcAddrImm<S>();
16281637
inst->setInidirectSource(
16291638
toSrcIx,
16301639
srcMod,
16311640
a0,
1632-
decodeSrcAddrImm<S>(),
1641+
addr_imm,
16331642
decRgn,
16341643
decodeSrcType<S>());
16351644
} else { // == GED_ADDR_MODE_INVALID
@@ -1810,10 +1819,16 @@ DecoderBase::decodeTernarySrcImmVal(Type t)
18101819
return val;
18111820
}
18121821

1822+
uint32_t DecoderBase::binNumToSubRegNum(
1823+
uint32_t binNum, RegName regName, Type type, bool isTernaryOrBranch)
1824+
{
1825+
return BytesOffsetToSubReg(binNum, regName, type);
1826+
}
1827+
18131828
void DecoderBase::decodeOptions(Instruction *inst)
18141829
{
18151830
const OpSpec &os = inst->getOpSpec();
1816-
if (os.supportsAccWrEn()) {
1831+
if (os.supportsAccWrEn(m_model.platform)) {
18171832
// * GED doesn't allow AccWrEn on send's
18181833
// * BrnchCtrl overlaps AccWrEn, so anything using that is out
18191834
GED_ACC_WR_CTRL accWrEn = GED_ACC_WR_CTRL_Normal;

‎visa/iga/IGALibrary/Backend/GED/Decoder.hpp

Lines changed: 8 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -79,6 +79,7 @@ namespace iga
7979
GED_ACCESS_MODE decodeAccessMode();
8080
MaskCtrl decodeMaskCtrl();
8181
Predication decodePredication();
82+
void decodePredInv(Predication& pred);
8283
FlagRegInfo decodeFlagRegInfo(bool imm64Src0Overlap = false); // pred, cond, ...
8384
ExecSize decodeExecSize();
8485
ChannelOffset decodeChannelOffset();
@@ -284,8 +285,9 @@ namespace iga
284285
scalingType = m_opSpec->isBranching() ? Type::D : Type::UB;
285286
}
286287

287-
dri.regRef.subRegNum = BytesOffsetToSubReg(
288-
dri.regRef.subRegNum, dri.regName, scalingType);
288+
dri.regRef.subRegNum = binNumToSubRegNum(
289+
dri.regRef.subRegNum, dri.regName,
290+
scalingType, m_opSpec->isBranching() || m_opSpec->isTernary());
289291

290292
return dri;
291293
}
@@ -309,6 +311,10 @@ namespace iga
309311

310312
void decodeOptions(Instruction *inst);
311313

314+
// Translate Sub register from binary encoding number to asm number
315+
uint32_t binNumToSubRegNum(
316+
uint32_t binNum, RegName regName, Type type, bool isTernaryOrBranch);
317+
312318
protected:
313319
GED_MODEL m_gedModel;
314320

‎visa/iga/IGALibrary/Backend/GED/Encoder.cpp

Lines changed: 51 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -329,17 +329,10 @@ void EncoderBase::encodeInstruction(Instruction& inst)
329329

330330
GED_ENCODE(MaskCtrl, IGAToGEDTranslation::lowerEmask(inst.getMaskCtrl()));
331331

332-
// GED_ExecutionDataType
332+
// Predicate
333333
const Predication &pred = inst.getPredication();
334-
RegRef flagReg = inst.getFlagReg();
335-
if (flagReg != REGREF_INVALID) {
336-
GED_ENCODE(FlagRegNum, static_cast<uint32_t>(inst.getFlagReg().regNum));
337-
GED_ENCODE(FlagSubRegNum, inst.getFlagReg().subRegNum);
338-
}
339-
340334
if (os.supportsPredication()) {
341335
GED_ENCODE(PredCtrl, IGAToGEDTranslation::lowerPredCtrl(pred.function));
342-
GED_ENCODE(PredInv, pred.inverse ? GED_PRED_INV_Invert : GED_PRED_INV_Normal);
343336
} else {
344337
GED_ENCODE(PredCtrl, GED_PRED_CTRL_Normal);
345338
}
@@ -352,6 +345,18 @@ void EncoderBase::encodeInstruction(Instruction& inst)
352345
}
353346
}
354347

348+
bool hasFlagRegField = true;
349+
350+
if (os.supportsPredication() && hasFlagRegField)
351+
GED_ENCODE(PredInv, pred.inverse ? GED_PRED_INV_Invert : GED_PRED_INV_Normal);
352+
353+
// GED_ExecutionDataType
354+
RegRef flagReg = inst.getFlagReg();
355+
if (hasFlagRegField && (flagReg != REGREF_INVALID)) {
356+
GED_ENCODE(FlagRegNum, static_cast<uint32_t>(inst.getFlagReg().regNum));
357+
GED_ENCODE(FlagSubRegNum, inst.getFlagReg().subRegNum);
358+
}
359+
355360
// set AccWrEn where supported
356361
if (inst.hasInstOpt(InstOpt::ACCWREN)) {
357362
GED_ENCODE(AccWrCtrl, GED_ACC_WR_CTRL_AccWrEn);
@@ -428,9 +433,8 @@ void EncoderBase::encodeTernaryDestinationAlign1(
428433
GED_ENCODE(DstMathMacroExt, IGAToGEDTranslation::lowerMathMacroReg(dst.getMathMacroExt()));
429434
// GED_ENCODE(DstHorzStride, 1);
430435
} else {
431-
uint32_t subRegNum = SubRegToBytesOffset(
432-
dst.getDirRegRef().subRegNum, dst.getDirRegName(), dst.getType());
433-
GED_ENCODE(DstSubRegNum, subRegNum);
436+
encodeDstSubRegNum(subRegNumToBinNum(
437+
dst.getDirRegRef().subRegNum, dst.getDirRegName(), dst.getType()), true);
434438
bool hasDstRgnHz = true;
435439
if (hasDstRgnHz) {
436440
GED_ENCODE(DstHorzStride, static_cast<int>(dst.getRegion().getHz()));
@@ -495,9 +499,9 @@ void EncoderBase::encodeTernarySourceAlign1(
495499
encodeSrcRegionHorz<S>(Region::Horz::HZ_1);
496500

497501
} else {
498-
uint32_t subRegNum = SubRegToBytesOffset(
502+
auto subReg = subRegNumToBinNum(
499503
src.getDirRegRef().subRegNum, src.getDirRegName(), src.getType());
500-
encodeSrcSubRegNum<S>(subRegNum);
504+
encodeSrcSubRegNum<S>(subReg, true);
501505
}
502506
break;
503507
}
@@ -841,11 +845,11 @@ void EncoderBase::encodeBranchDestination(
841845
GED_ENCODE(DstRegFile,
842846
IGAToGEDTranslation::lowerRegFile(dst.getDirRegName()));
843847
encodeDstReg(dst.getDirRegName(), dst.getDirRegRef().regNum);
844-
GED_ENCODE(DstSubRegNum,
845-
SubRegToBytesOffset(
846-
dst.getDirRegRef().subRegNum,
847-
dst.getDirRegName(),
848-
dst.getType()));
848+
encodeDstSubRegNum(subRegNumToBinNum(
849+
dst.getDirRegRef().subRegNum,
850+
dst.getDirRegName(),
851+
dst.getType()),
852+
true);
849853
}
850854

851855
void EncoderBase::encodeBasicDestination(
@@ -911,12 +915,14 @@ void EncoderBase::encodeBasicDestination(
911915
encodeDstReg(dst.getDirRegName(), dst.getDirRegRef().regNum);
912916
GED_ENCODE(DstChanEn, GED_DST_CHAN_EN_xyzw);
913917
}
914-
GED_ENCODE(DstSubRegNum,
915-
SubRegToBytesOffset(dst.getDirRegRef().subRegNum, dst.getDirRegName(), dst.getType()));
918+
encodeDstSubRegNum(
919+
subRegNumToBinNum(dst.getDirRegRef().subRegNum, dst.getDirRegName(), dst.getType()),
920+
inst.getOpSpec().isTernary() || inst.getOpSpec().isBranching());
916921
} else { // Align1
917922
encodeDstReg(dst.getDirRegName(), dst.getDirRegRef().regNum);
918-
GED_ENCODE(DstSubRegNum,
919-
SubRegToBytesOffset(dst.getDirRegRef().subRegNum, dst.getDirRegName(), dst.getType()));
923+
encodeDstSubRegNum(
924+
subRegNumToBinNum(dst.getDirRegRef().subRegNum, dst.getDirRegName(), dst.getType()),
925+
inst.getOpSpec().isTernary() || inst.getOpSpec().isBranching());
920926
}
921927
break;
922928
case Operand::Kind::MACRO:
@@ -971,9 +977,9 @@ void EncoderBase::encodeBranchSource(
971977
{
972978
encodeSrcRegFile<SourceIndex::SRC0>(IGAToGEDTranslation::lowerRegFile(src.getDirRegName()));
973979
encodeSrcReg<SourceIndex::SRC0>(src.getDirRegName(),src.getDirRegRef().regNum);
974-
uint32_t subRegBits = SubRegToBytesOffset(
980+
auto subReg = subRegNumToBinNum(
975981
src.getDirRegRef().subRegNum, src.getDirRegName(), Type::D);
976-
encodeSrcSubRegNum<SourceIndex::SRC0>(subRegBits);
982+
encodeSrcSubRegNum<SourceIndex::SRC0>(subReg, true);
977983
}
978984

979985
template <SourceIndex S>
@@ -1016,9 +1022,10 @@ void EncoderBase::encodeBasicSource(
10161022
encodeSrcReg<S>(RegName::ARF_MME, 0);
10171023
} else {
10181024
encodeSrcReg<S>(src.getDirRegName(), src.getDirRegRef().regNum);
1019-
uint32_t subRegBits = SubRegToBytesOffset(
1025+
auto subReg = subRegNumToBinNum(
10201026
src.getDirRegRef().subRegNum, src.getDirRegName(), src.getType());
1021-
encodeSrcSubRegNum<S>(subRegBits);
1027+
encodeSrcSubRegNum<S>(subReg,
1028+
inst.getOpSpec().isTernary() || inst.getOpSpec().isBranching());
10221029
}
10231030
} else { // (src.getKind() == Operand::Kind::MACRO)
10241031
encodeSrcReg<S>(RegName::GRF_R,src.getDirRegRef().regNum);
@@ -1216,8 +1223,8 @@ void EncoderBase::encodeSendSource0(const Operand& src)
12161223
else if( src.getKind() == Operand::Kind::INDIRECT )
12171224
{
12181225
GED_ENCODE(Src0DataType, IGAToGEDTranslation::lowerDataType(t));
1219-
GED_ENCODE(Src0AddrImm, src.getIndImmAddr());
12201226
GED_ENCODE(Src0AddrSubRegNum, src.getIndAddrReg().subRegNum);
1227+
GED_ENCODE(Src0AddrImm, src.getIndImmAddr());
12211228
}
12221229
}
12231230

@@ -1276,8 +1283,8 @@ void EncoderBase::encodeSendsDestination(const Operand& dst)
12761283

12771284
GED_ENCODE(DstRegNum, dst.getDirRegRef().regNum);
12781285
//TODO: set correct regType
1279-
GED_ENCODE(DstSubRegNum,
1280-
SubRegToBytesOffset(dst.getDirRegRef().subRegNum, RegName::GRF_R, dst.getType()));
1286+
encodeDstSubRegNum(
1287+
subRegNumToBinNum(dst.getDirRegRef().subRegNum, RegName::GRF_R, dst.getType()), true);
12811288
}
12821289

12831290
template <SourceIndex S>
@@ -1366,9 +1373,9 @@ void EncoderBase::encodeTernarySourceAlign16(const Instruction& inst)
13661373
}
13671374
uint32_t regNum = reg.regNum;
13681375
encodeSrcReg<S>(RegName::GRF_R,regNum);
1369-
uint32_t subRegNum =
1370-
SubRegToBytesOffset(subRegNumber, src.getDirRegName(), src.getType());
1371-
encodeSrcSubRegNum<S>(subRegNum);
1376+
auto subReg =
1377+
subRegNumToBinNum(subRegNumber, src.getDirRegName(), src.getType());
1378+
encodeSrcSubRegNum<S>(subReg, true);
13721379
} else {
13731380
// implicit operand accumulator
13741381
// e.g. madm (4) ... -r14.acc3
@@ -1446,9 +1453,8 @@ void EncoderBase::encodeTernaryDestinationAlign16(const Instruction& inst)
14461453
}
14471454
}
14481455
GED_ENCODE(DstChanEn, chanEn);
1449-
uint32_t subRegNum = SubRegToBytesOffset(
1450-
reg.subRegNum, dst.getDirRegName(), dst.getType());
1451-
GED_ENCODE(DstSubRegNum, subRegNum);
1456+
encodeDstSubRegNum(subRegNumToBinNum(
1457+
reg.subRegNum, dst.getDirRegName(), dst.getType()), true);
14521458
}
14531459
}
14541460

@@ -1568,6 +1574,16 @@ void EncoderBase::encodeOptionsThreadControl(const Instruction& inst)
15681574
}
15691575
}
15701576

1577+
// Translate from subRegNum to num represented in binary encoding
1578+
std::pair<bool, uint32_t> EncoderBase::subRegNumToBinNum(int subRegNum, RegName regName, Type type)
1579+
{
1580+
return std::make_pair(true, SubRegToBytesOffset(subRegNum, regName, type));
1581+
}
1582+
1583+
void EncoderBase::encodeDstSubRegNum(std::pair<bool, uint32_t> subReg, bool isTernaryOrBranch)
1584+
{
1585+
GED_ENCODE(DstSubRegNum, subReg.second);
1586+
}
15711587

15721588
void EncoderBase::encodeOptions(const Instruction& inst)
15731589
{

‎visa/iga/IGALibrary/Backend/GED/Encoder.hpp

Lines changed: 13 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -93,7 +93,8 @@ namespace iga
9393
template <SourceIndex S> void encodeSrcType(Type t);
9494
template <SourceIndex S> void encodeSrcAddrMode(GED_ADDR_MODE x);
9595
template <SourceIndex S> void encodeSrcModifier(SrcModifier x);
96-
template <SourceIndex S> void encodeSrcSubRegNum(uint32_t subReg);
96+
template <SourceIndex S> void encodeSrcSubRegNum(
97+
std::pair<bool, uint32_t> subReg, bool isTernaryOrBranch);
9798

9899
template <SourceIndex S> void encodeSrcMathMacroReg(MathMacroExt a);
99100

@@ -195,6 +196,12 @@ namespace iga
195196
void applyGedWorkarounds(const Kernel &k, size_t bitsLen);
196197
void encodeOptions(const Instruction& inst);
197198

199+
// Translate from subRegNum to num represented in binary encoding.
200+
// Return std::pair<bool, uint32_t> the bool denotes if the given sub reg num is
201+
// aligned to binary offset representation
202+
std::pair<bool, uint32_t> subRegNumToBinNum(int subRegNum, RegName regName, Type type);
203+
void encodeDstSubRegNum(std::pair<bool, uint32_t> subReg, bool isTernaryOrBranch);
204+
198205
//////////////////////////////////////////////////////////////////////
199206
// platform specific queries *but sometimes need the instruction too)
200207
//
@@ -342,13 +349,14 @@ namespace iga
342349
}
343350
}
344351

345-
template <SourceIndex S> void EncoderBase::encodeSrcSubRegNum(uint32_t subReg) {
352+
template <SourceIndex S> void EncoderBase::encodeSrcSubRegNum(
353+
std::pair<bool, uint32_t> subReg, bool isTernaryOrBranch) {
346354
if (S == SourceIndex::SRC0) {
347-
GED_ENCODE(Src0SubRegNum, subReg);
355+
GED_ENCODE(Src0SubRegNum, subReg.second);
348356
} else if (S == SourceIndex::SRC1) {
349-
GED_ENCODE(Src1SubRegNum, subReg);
357+
GED_ENCODE(Src1SubRegNum, subReg.second);
350358
} else {
351-
GED_ENCODE(Src2SubRegNum, subReg);
359+
GED_ENCODE(Src2SubRegNum, subReg.second);
352360
}
353361
}
354362

‎visa/iga/IGALibrary/Backend/Native/InstEncoder.hpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -490,7 +490,7 @@ namespace iga
490490
case RegName::GRF_R:
491491
case RegName::ARF_ACC:
492492
case RegName::ARF_A:
493-
if (val > 32) {
493+
if (val > 64) {
494494
encodingError(f, "subregister out of bounds");
495495
}
496496
break;

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