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Fix neg and not opts.
1 parent 6f20e4e commit b165d7b

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2 files changed

+23
-8
lines changed

2 files changed

+23
-8
lines changed

llvm/lib/Target/Z80/GISel/Z80LegalizerInfo.cpp

Lines changed: 21 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -104,8 +104,8 @@ Z80LegalizerInfo::Z80LegalizerInfo(const Z80Subtarget &STI,
104104
.clampScalar(1, s8, sMax);
105105

106106
getActionDefinitionsBuilder({G_ADD, G_SUB})
107-
.legalFor(LegalScalars)
108-
.customFor({s32, s64})
107+
.legalFor({s8})
108+
.customFor(LegalLibcallScalars)
109109
.clampScalar(0, s8, sMax);
110110

111111
getActionDefinitionsBuilder({G_UADDO, G_UADDE, G_USUBO, G_USUBE,
@@ -288,14 +288,18 @@ Z80LegalizerInfo::legalizeAddSub(LegalizerHelper &Helper, MachineInstr &MI,
288288
LostDebugLocObserver &LocObserver) const {
289289
assert((MI.getOpcode() == G_ADD || MI.getOpcode() == G_SUB) &&
290290
"Unexpected opcode");
291+
Function &F = Helper.MIRBuilder.getMF().getFunction();
291292
MachineRegisterInfo &MRI = *Helper.MIRBuilder.getMRI();
292293
Register DstReg = MI.getOperand(0).getReg();
293294
LLT LLTy = MRI.getType(DstReg);
295+
unsigned Size = LLTy.getSizeInBits();
296+
bool LegalSize = Size == 16 || (Subtarget.is24Bit() && Size == 24);
294297
Register LHSReg;
295298
if (mi_match(MI, MRI, m_Neg(m_Reg(LHSReg)))) {
296-
auto &Ctx = Helper.MIRBuilder.getMF().getFunction().getContext();
299+
if (!F.hasOptSize() && LegalSize)
300+
return LegalizerHelper::Legalized;
301+
auto &Ctx = F.getContext();
297302
RTLIB::Libcall Libcall;
298-
unsigned Size = LLTy.getSizeInBits();
299303
switch (Size) {
300304
case 16:
301305
Libcall = RTLIB::NEG_I16;
@@ -318,6 +322,8 @@ Z80LegalizerInfo::legalizeAddSub(LegalizerHelper &Helper, MachineInstr &MI,
318322
MI.eraseFromParent();
319323
return LegalizerHelper::Legalized;
320324
}
325+
if (LegalSize)
326+
return LegalizerHelper::Legalized;
321327
return Helper.libcall(MI, LocObserver);
322328
}
323329

@@ -327,18 +333,26 @@ Z80LegalizerInfo::legalizeBitwise(LegalizerHelper &Helper, MachineInstr &MI,
327333
assert((MI.getOpcode() == G_AND || MI.getOpcode() == G_OR ||
328334
MI.getOpcode() == G_XOR) &&
329335
"Unexpected opcode");
336+
Function &F = Helper.MIRBuilder.getMF().getFunction();
337+
bool OptSize = F.hasOptSize();
330338
MachineRegisterInfo &MRI = *Helper.MIRBuilder.getMRI();
331339
Register DstReg = MI.getOperand(0).getReg();
332340
LLT LLTy = MRI.getType(DstReg);
333-
if (!MI.getParent()->getParent()->getFunction().hasOptSize() &&
334-
LLTy == LLT::scalar(16))
341+
if (!OptSize && LLTy == LLT::scalar(16))
335342
if (Helper.narrowScalar(MI, 0, LLT::scalar(8)) ==
336343
LegalizerHelper::Legalized)
337344
return LegalizerHelper::Legalized;
338345
Register LHSReg;
339346
if (mi_match(MI, MRI, m_Not(m_Reg(LHSReg)))) {
340-
auto &Ctx = Helper.MIRBuilder.getMF().getFunction().getContext();
341347
unsigned Size = LLTy.getSizeInBits();
348+
if (!OptSize && (Size == 16 || (Subtarget.is24Bit() && Size == 24))) {
349+
Helper.MIRBuilder.buildSub(DstReg,
350+
Helper.MIRBuilder.buildConstant(LLTy, -1),
351+
MI.getOperand(1).getReg());
352+
MI.eraseFromParent();
353+
return LegalizerHelper::Legalized;
354+
}
355+
auto &Ctx = F.getContext();
342356
RTLIB::Libcall Libcall;
343357
switch (Size) {
344358
case 16:

llvm/lib/Target/Z80/Z80InstrInfo.td

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -400,7 +400,8 @@ let isMoveImm = 1, isReMaterializable = 1 in {
400400
def LD24r0 : Pseudo<"ld", "\t$dst, 0", "",
401401
(outs R24:$dst), (ins), [(set R24:$dst, 0)]>;
402402
def LD24r_1 : Pseudo<"ld", "\t$dst, -1", "",
403-
(outs R24:$dst), (ins), [(set R24:$dst, -1)]>;
403+
(outs R24:$dst), (ins), [(set R24:$dst,
404+
!sub(!shl(1, 24), 1))]>;
404405
}
405406
def LD8ri : I8i <Idx0Pre, 0x06, "ld", "\t$dst, $src", "",
406407
(outs R8:$dst), (ins i8imm:$src),

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