From 3ea3709599466826bbb7835d80a4b8a6ea47bcae Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andr=C3=A9s=20Manelli?= Date: Thu, 11 Jul 2019 21:52:46 +0200 Subject: [PATCH 1/2] Add entity parsing --- hdlparse/vhdl_parser.py | 43 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 42 insertions(+), 1 deletion(-) diff --git a/hdlparse/vhdl_parser.py b/hdlparse/vhdl_parser.py index 6adb021..db785a2 100644 --- a/hdlparse/vhdl_parser.py +++ b/hdlparse/vhdl_parser.py @@ -84,7 +84,9 @@ (r'--.*\n', None), ], 'entity': [ - (r'end\s+entity\s*;', 'end_entity', '#pop'), + (r'generic\s*\(', None, 'generic_list'), + (r'port\s*\(', None, 'port_list'), + (r'end\s+\w+\s*;', 'end_entity', '#pop'), (r'/\*', 'block_comment', 'block_comment'), (r'--.*\n', None), ], @@ -290,6 +292,30 @@ def __init__(self, name, package, parameters, desc=None): def __repr__(self): return "VhdlProcedure('{}')".format(self.name) +class VhdlEntity(VhdlObject): + '''Entity declaration + + Args: + name (str): Name of the entity + ports (list of VhdlParameter): Port parameters to the entity + generics (list of VhdlParameter): Generic parameters to the entity + sections (list of str): Metacomment sections + desc (str, optional): Description from object metacomments + ''' + def __init__(self, name, ports, generics=None, sections=None, desc=None): + VhdlObject.__init__(self, name, desc) + self.kind = 'entity' + self.generics = generics if generics is not None else [] + self.ports = ports + self.sections = sections if sections is not None else {} + + def __repr__(self): + return "VhdlEntity('{}')".format(self.name) + + def dump(self): + print('VHDL entity: {}'.format(self.name)) + for p in self.ports: + print('\t{} ({}), {} ({})'.format(p.name, type(p.name), p.data_type, type(p.data_type))) class VhdlComponent(VhdlObject): '''Component declaration @@ -423,6 +449,15 @@ def parse_vhdl(text): kind = None name = None + elif action == 'entity': + kind = 'entity' + name = groups[0] + generics = [] + ports = [] + param_items = [] + sections = [] + port_param_index = 0 + elif action == 'component': kind = 'component' name = groups[0] @@ -469,6 +504,12 @@ def parse_vhdl(text): param_items = [] last_item = ports[-1] + elif action == 'end_entity': + vobj = VhdlEntity(name, ports, generics, dict(sections), metacomments) + objects.append(vobj) + last_item = None + metacomments = [] + elif action == 'end_component': vobj = VhdlComponent(name, cur_package, ports, generics, dict(sections), metacomments) objects.append(vobj) From 21b54a6f158ce761d90a1199317ff3ac456a7e27 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andr=C3=A9s=20Manelli?= Date: Thu, 11 Jul 2019 22:31:30 +0200 Subject: [PATCH 2/2] Add default values for ports and generics --- hdlparse/vhdl_parser.py | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/hdlparse/vhdl_parser.py b/hdlparse/vhdl_parser.py index db785a2..747eae3 100644 --- a/hdlparse/vhdl_parser.py +++ b/hdlparse/vhdl_parser.py @@ -478,6 +478,9 @@ def parse_vhdl(text): param_items = [] last_item = generics[-1] + elif action == 'generic_param_default': + last_item.default_value = groups[0] + elif action == 'port_param': param_items.append(groups[0]) port_param_index += 1 @@ -491,6 +494,9 @@ def parse_vhdl(text): param_items = [] last_item = ports[-1] + elif action == 'port_param_default': + last_item.default_value = groups[0] + elif action == 'port_array_param_type': mode, ptype = groups array_range_start_pos = pos[1]