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Directly checking for S_XOR_B32
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llvm/lib/Target/AMDGPU/SIISelLowering.cpp

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -5258,18 +5258,18 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
52585258
case AMDGPU::S_MAX_U32:
52595259
case AMDGPU::S_MAX_I32:
52605260
case AMDGPU::S_AND_B32:
5261-
case AMDGPU::S_AND_B64:
5262-
case AMDGPU::S_OR_B32:
5263-
case AMDGPU::S_OR_B64: {
5261+
case AMDGPU::S_OR_B32: {
52645262
// Idempotent operations.
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BuildMI(BB, MI, DL, TII->get(AMDGPU::S_MOV_B32), DstReg).addReg(SrcReg);
52665264
RetBB = &BB;
52675265
break;
52685266
}
5269-
case AMDGPU::V_CMP_LT_U64_e64: // umin
5270-
case AMDGPU::V_CMP_LT_I64_e64: // min
5271-
case AMDGPU::V_CMP_GT_U64_e64: // umax
5272-
case AMDGPU::V_CMP_GT_I64_e64: { // max
5267+
case AMDGPU::V_CMP_LT_U64_e64: // umin
5268+
case AMDGPU::V_CMP_LT_I64_e64: // min
5269+
case AMDGPU::V_CMP_GT_U64_e64: // umax
5270+
case AMDGPU::V_CMP_GT_I64_e64: // max
5271+
case AMDGPU::S_AND_B64:
5272+
case AMDGPU::S_OR_B64: {
52735273
// Idempotent operations.
52745274
BuildMI(BB, MI, DL, TII->get(AMDGPU::S_MOV_B64), DstReg).addReg(SrcReg);
52755275
RetBB = &BB;
@@ -5313,7 +5313,7 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
53135313
.addReg(NewAccumulator->getOperand(0).getReg())
53145314
.addImm(1)
53155315
.setOperandDead(3); // Dead scc
5316-
if (is32BitOpc) {
5316+
if (Opc == AMDGPU::S_XOR_B32) {
53175317
BuildMI(BB, MI, DL, TII->get(AMDGPU::S_MUL_I32), DstReg)
53185318
.addReg(SrcReg)
53195319
.addReg(ParityRegister);

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