@@ -5258,18 +5258,18 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
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case AMDGPU::S_MAX_U32:
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case AMDGPU::S_MAX_I32:
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case AMDGPU::S_AND_B32:
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- case AMDGPU::S_AND_B64:
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- case AMDGPU::S_OR_B32:
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- case AMDGPU::S_OR_B64: {
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+ case AMDGPU::S_OR_B32: {
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// Idempotent operations.
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BuildMI(BB, MI, DL, TII->get(AMDGPU::S_MOV_B32), DstReg).addReg(SrcReg);
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RetBB = &BB;
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break;
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}
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- case AMDGPU::V_CMP_LT_U64_e64: // umin
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- case AMDGPU::V_CMP_LT_I64_e64: // min
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- case AMDGPU::V_CMP_GT_U64_e64: // umax
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- case AMDGPU::V_CMP_GT_I64_e64: { // max
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+ case AMDGPU::V_CMP_LT_U64_e64: // umin
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+ case AMDGPU::V_CMP_LT_I64_e64: // min
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+ case AMDGPU::V_CMP_GT_U64_e64: // umax
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+ case AMDGPU::V_CMP_GT_I64_e64: // max
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+ case AMDGPU::S_AND_B64:
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+ case AMDGPU::S_OR_B64: {
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// Idempotent operations.
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BuildMI(BB, MI, DL, TII->get(AMDGPU::S_MOV_B64), DstReg).addReg(SrcReg);
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RetBB = &BB;
@@ -5313,7 +5313,7 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
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.addReg(NewAccumulator->getOperand(0).getReg())
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.addImm(1)
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.setOperandDead(3); // Dead scc
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- if (is32BitOpc ) {
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+ if (Opc == AMDGPU::S_XOR_B32 ) {
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BuildMI(BB, MI, DL, TII->get(AMDGPU::S_MUL_I32), DstReg)
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.addReg(SrcReg)
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.addReg(ParityRegister);
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