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[DAG][ARM] ComputeKnownBitsForTargetNode - add handling for ARMISD VORRIMM\VBICIMM nodes (#149494)
### Summary This PR resolves #147179
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‎llvm/lib/Target/ARM/ARMISelLowering.cpp‎

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@@ -20065,6 +20065,29 @@ void ARMTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
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Known = KnownOp0.intersectWith(KnownOp1);
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break;
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}
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case ARMISD::VORRIMM:
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case ARMISD::VBICIMM: {
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unsigned Encoded = Op.getConstantOperandVal(1);
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unsigned DecEltBits = 0;
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uint64_t DecodedVal = ARM_AM::decodeVMOVModImm(Encoded, DecEltBits);
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unsigned EltBits = Op.getScalarValueSizeInBits();
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if (EltBits != DecEltBits) {
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// Be conservative: only update Known when EltBits == DecEltBits.
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// This is believed to always be true for VORRIMM/VBICIMM today, but if
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// that changes in the future, doing nothing here is safer than risking
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// subtle bugs.
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break;
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}
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KnownBits KnownLHS = DAG.computeKnownBits(Op.getOperand(0), Depth + 1);
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bool IsVORR = Op.getOpcode() == ARMISD::VORRIMM;
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APInt Imm(DecEltBits, DecodedVal);
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Known.One = IsVORR ? (KnownLHS.One | Imm) : (KnownLHS.One & ~Imm);
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Known.Zero = IsVORR ? (KnownLHS.Zero & ~Imm) : (KnownLHS.Zero | Imm);
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break;
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}
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}
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}
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‎llvm/unittests/Target/ARM/ARMSelectionDAGTest.cpp‎

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//===----------------------------------------------------------------------===//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "ARMISelLowering.h"
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#include "MCTargetDesc/ARMAddressingModes.h"
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#include "llvm/Analysis/OptimizationRemarkEmitter.h"
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#include "llvm/AsmParser/Parser.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/TargetLowering.h"
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#include "llvm/IR/MDBuilder.h"
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#include "llvm/IR/Module.h"
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#include "llvm/MC/TargetRegistry.h"
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#include "llvm/Support/KnownBits.h"
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#include "llvm/Support/SourceMgr.h"
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#include "llvm/Support/TargetSelect.h"
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#include "llvm/Target/TargetMachine.h"
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#include "gtest/gtest.h"
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namespace llvm {
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class ARMSelectionDAGTest : public testing::Test {
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protected:
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static void SetUpTestCase() {
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LLVMInitializeARMTargetInfo();
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LLVMInitializeARMTarget();
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LLVMInitializeARMTargetMC();
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}
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void SetUp() override {
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StringRef Assembly = "define void @f() { ret void }";
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Triple TargetTriple("armv7-unknown-none-eabi");
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std::string Error;
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const Target *T = TargetRegistry::lookupTarget("", TargetTriple, Error);
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TargetOptions Options;
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TM = std::unique_ptr<TargetMachine>(
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T->createTargetMachine(TargetTriple,
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/*CPU*/ "cortex-a9",
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/*Features*/ "+neon", Options, std::nullopt,
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std::nullopt, CodeGenOptLevel::Aggressive));
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SMDiagnostic SMError;
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M = parseAssemblyString(Assembly, SMError, Context);
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if (!M)
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report_fatal_error(SMError.getMessage());
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M->setDataLayout(TM->createDataLayout());
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F = M->getFunction("f");
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if (!F)
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report_fatal_error("Function 'f' not found");
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MachineModuleInfo MMI(TM.get());
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MF = std::make_unique<MachineFunction>(*F, *TM, *TM->getSubtargetImpl(*F),
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MMI.getContext(), /*FunctionNum*/ 0);
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DAG = std::make_unique<SelectionDAG>(*TM, CodeGenOptLevel::None);
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if (!DAG)
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report_fatal_error("SelectionDAG allocation failed");
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OptimizationRemarkEmitter ORE(F);
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DAG->init(*MF, ORE, /*LibInfo*/ nullptr, /*AA*/ nullptr,
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/*AC*/ nullptr, /*MDT*/ nullptr, /*MSDT*/ nullptr, MMI, nullptr);
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}
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TargetLoweringBase::LegalizeTypeAction getTypeAction(EVT VT) {
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return DAG->getTargetLoweringInfo().getTypeAction(Context, VT);
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}
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EVT getTypeToTransformTo(EVT VT) {
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return DAG->getTargetLoweringInfo().getTypeToTransformTo(Context, VT);
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}
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LLVMContext Context;
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std::unique_ptr<TargetMachine> TM;
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std::unique_ptr<Module> M;
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Function *F = nullptr;
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std::unique_ptr<MachineFunction> MF;
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std::unique_ptr<SelectionDAG> DAG;
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};
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/// VORR (immediate): per-lane OR with 32-bit elements.
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/// cmode=0x0 puts imm8 in byte0 => per-lane constant = 0x000000AA.
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TEST_F(ARMSelectionDAGTest, computeKnownBits_VORRIMM) {
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SDLoc DL;
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EVT VT = MVT::v4i32;
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SDValue LHS = DAG->getRegister(0, VT);
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SDValue EncSD =
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DAG->getTargetConstant(ARM_AM::createVMOVModImm(0x0, 0xAA), DL, MVT::i32);
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SDValue Op = DAG->getNode(ARMISD::VORRIMM, DL, VT, LHS, EncSD);
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// LHS(per-lane) = ???????? ???????? ???????? ????????
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// Encoded(per-lane) = 00000000 00000000 00000000 10101010 (0x000000AA)
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// =>
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// Known.One = 00000000 00000000 00000000 10101010 (0x000000AA)
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// Known.Zero = 00000000 00000000 00000000 00000000 (0x00000000)
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APInt DemandedElts = APInt::getAllOnes(4);
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KnownBits Known = DAG->computeKnownBits(Op, DemandedElts);
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EXPECT_EQ(Known.One, APInt(32, 0xAA));
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EXPECT_EQ(Known.Zero, APInt(32, 0x0));
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}
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/// VBIC (immediate): x & ~imm with 32-bit elements.
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/// LHS(per-lane)=0xFFFFFFFF; imm per-lane = 0x000000AA => result = 0xFFFFFF55
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TEST_F(ARMSelectionDAGTest, computeKnownBits_VBICIMM) {
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SDLoc DL;
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EVT VT = MVT::v4i32;
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SDValue LHS = DAG->getConstant(APInt(32, 0xFFFFFFFF), DL, VT);
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SDValue EncSD =
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DAG->getTargetConstant(ARM_AM::createVMOVModImm(0x0, 0xAA), DL, MVT::i32);
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SDValue Op = DAG->getNode(ARMISD::VBICIMM, DL, VT, LHS, EncSD);
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// LHS(per-lane) = 11111111 11111111 11111111 11111111 (0xFFFFFFFF)
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// Encoded(per-lane) = 00000000 00000000 00000000 10101010 (0x000000AA)
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// =>
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// Known.One = 11111111 11111111 11111111 01010101 (0xFFFFFF55)
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// Known.Zero = 00000000 00000000 00000000 10101010 (0x000000AA)
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APInt DemandedElts = APInt::getAllOnes(4);
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KnownBits Known = DAG->computeKnownBits(Op, DemandedElts);
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EXPECT_EQ(Known.One, APInt(32, 0xFFFFFF55));
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EXPECT_EQ(Known.Zero, APInt(32, 0x000000AA));
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}
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/// VORR (immediate): per-lane OR with 32-bit elements.
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/// Encoded = 0x2AA (cmode=0x2, imm8=0xAA) => per-lane constant = 0x0000AA00.
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TEST_F(ARMSelectionDAGTest, computeKnownBits_VORRIMM_cmode2) {
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SDLoc DL;
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EVT VT = MVT::v4i32;
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SDValue LHS = DAG->getRegister(0, VT);
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// Use the exact encoded immediate the reviewer asked for.
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SDValue EncSD =
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DAG->getTargetConstant(ARM_AM::createVMOVModImm(0x2, 0xAA), DL, MVT::i32);
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SDValue Op = DAG->getNode(ARMISD::VORRIMM, DL, VT, LHS, EncSD);
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// LHS (per-lane) = ???????? ???????? ???????? ????????
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// Encoded (per-lane) = 00000000 00000000 10101010 00000000 (0x0000AA00)
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// =>
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// Known.One = 00000000 00000000 10101010 00000000 (0x0000AA00)
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// Known.Zero = 00000000 00000000 00000000 00000000 (0x00000000)
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APInt DemandedElts = APInt::getAllOnes(4);
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KnownBits Known = DAG->computeKnownBits(Op, DemandedElts);
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EXPECT_EQ(Known.One, APInt(32, 0x0000AA00));
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EXPECT_EQ(Known.Zero, APInt(32, 0x00000000));
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}
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/// VBIC (immediate) with constant-all-ones LHS:
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/// Encoded = 0x2AA => per-lane constant = 0x0000AA00; VBIC = A & ~Imm.
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TEST_F(ARMSelectionDAGTest, computeKnownBits_VBICIMM_cmode2_lhs_ones) {
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SDLoc DL;
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EVT VT = MVT::v4i32;
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SDValue LHS = DAG->getConstant(APInt(32, 0xFFFFFFFF), DL, VT);
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SDValue EncSD =
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DAG->getTargetConstant(ARM_AM::createVMOVModImm(0x2, 0xAA), DL, MVT::i32);
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SDValue Op = DAG->getNode(ARMISD::VBICIMM, DL, VT, LHS, EncSD);
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// LHS (per-lane) = 11111111 11111111 11111111 11111111
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// Encoded (per-lane) = 00000000 00000000 10101010 00000000 (0x0000AA00)
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// =>
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// Known.One = 11111111 11111111 01010101 11111111 (0xFFFF55FF)
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// Known.Zero = 00000000 00000000 10101010 00000000 (0x0000AA00)
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APInt DemandedElts = APInt::getAllOnes(4);
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KnownBits Known = DAG->computeKnownBits(Op, DemandedElts);
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EXPECT_EQ(Known.One, APInt(32, 0xFFFF55FF));
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EXPECT_EQ(Known.Zero, APInt(32, 0x0000AA00));
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}
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} // end namespace llvm

‎llvm/unittests/Target/ARM/CMakeLists.txt‎

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@@ -22,4 +22,5 @@ set(LLVM_LINK_COMPONENTS
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add_llvm_target_unittest(ARMTests
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MachineInstrTest.cpp
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InstSizes.cpp
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ARMSelectionDAGTest.cpp
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)

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