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Getting negated value using S_SUB_I32 in place of S_MUL_I32.
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+73
-74
lines changed

2 files changed

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-74
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llvm/lib/Target/AMDGPU/SIISelLowering.cpp

Lines changed: 13 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -5244,13 +5244,13 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
52445244
.addImm(AMDGPU::sub1);
52455245
break;
52465246
}
5247-
}
5247+
}
52485248
case AMDGPU::S_SUB_I32: {
52495249
Register NegatedVal = MRI.createVirtualRegister(DstRegClass);
52505250

52515251
// Take the negation of the source operand.
5252-
BuildMI(BB, MI, DL, TII->get(AMDGPU::S_MUL_I32), NegatedVal)
5253-
.addImm(-1)
5252+
BuildMI(BB, MI, DL, TII->get(AMDGPU::S_SUB_I32), NegatedVal)
5253+
.addImm(0)
52545254
.addReg(SrcReg);
52555255
BuildMI(BB, MI, DL, TII->get(AMDGPU::S_MUL_I32), DstReg)
52565256
.addReg(NegatedVal)
@@ -5288,17 +5288,16 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
52885288
MI, MRI, MI.getOperand(1), Src1RC, AMDGPU::sub1, Src1SubRC);
52895289

52905290
if (Opc == AMDGPU::S_SUB_U64_PSEUDO) {
5291-
BuildMI(BB, MI, DL, TII->get(AMDGPU::S_MUL_I32), NegatedValLo)
5292-
.addReg(NewAccumulator->getOperand(0).getReg())
5293-
.addImm(-1);
5294-
5295-
BuildMI(BB, MI, DL, TII->get(AMDGPU::S_ASHR_I32), NegatedValHi)
5296-
.addReg(NegatedValLo)
5297-
.addImm(31)
5298-
.setOperandDead(3); // Dead scc
5299-
BuildMI(BB, MI, DL, TII->get(AMDGPU::S_MUL_I32), Op1L_Op0H_Reg)
5300-
.add(Op1L)
5301-
.addReg(NegatedValHi);
5291+
BuildMI(BB, MI, DL, TII->get(AMDGPU::S_SUB_I32), NegatedValLo)
5292+
.addImm(0)
5293+
.addReg(NewAccumulator->getOperand(0).getReg());
5294+
BuildMI(BB, MI, DL, TII->get(AMDGPU::S_ASHR_I32), NegatedValHi)
5295+
.addReg(NegatedValLo)
5296+
.addImm(31)
5297+
.setOperandDead(3); // Dead scc
5298+
BuildMI(BB, MI, DL, TII->get(AMDGPU::S_MUL_I32), Op1L_Op0H_Reg)
5299+
.add(Op1L)
5300+
.addReg(NegatedValHi);
53025301
}
53035302
Register LowOpcode = Opc == AMDGPU::S_SUB_U64_PSEUDO
53045303
? NegatedValLo

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