[CodeGen]Added support for COPY_LANEMASK instruction

This new instruction takes laneMask as an operand with
respect to the input operand storing the essential information.

Author: vg0204

llvm/include/llvm/CodeGen/MachineInstr.h

@@ -1429,7 +1429,8 @@ class MachineInstr
   }
 
   bool isCopy() const {
-    return getOpcode() == TargetOpcode::COPY;
+    return (getOpcode() == TargetOpcode::COPY ||
+            getOpcode() == TargetOpcode::COPY_LANEMASK);
   }
 
   bool isFullCopy() const {
@@ -1465,6 +1466,7 @@ class MachineInstr
     case TargetOpcode::PHI:
     case TargetOpcode::G_PHI:
     case TargetOpcode::COPY:
+    case TargetOpcode::COPY_LANEMASK:
     case TargetOpcode::INSERT_SUBREG:
     case TargetOpcode::SUBREG_TO_REG:
     case TargetOpcode::REG_SEQUENCE:

llvm/include/llvm/Support/TargetOpcodes.def

@@ -114,6 +114,11 @@ HANDLE_TARGET_OPCODE(REG_SEQUENCE)
 /// used to copy between subregisters of virtual registers.
 HANDLE_TARGET_OPCODE(COPY)
 
+/// COPY_LANEMASK - Target-independent register copy for active mask in 
+/// register as represented by the lanemask. This instruction can only be 
+/// used to copy between physical registers.
+HANDLE_TARGET_OPCODE(COPY_LANEMASK)
+
 /// BUNDLE - This instruction represents an instruction bundle. Instructions
 /// which immediately follow a BUNDLE instruction which are marked with
 /// 'InsideBundle' flag are inside the bundle.

llvm/include/llvm/Target/Target.td

@@ -1329,6 +1329,13 @@ def COPY : StandardPseudoInstruction {
   let isAsCheapAsAMove = true;
   let hasNoSchedulingInfo = false;
 }
+def COPY_LANEMASK : StandardPseudoInstruction {
+  let OutOperandList = (outs unknown:$dst);
+  let InOperandList = (ins unknown:$src, unknown:$lanemask);
+  let AsmString = "";
+  let hasSideEffects = false;
+  let isAsCheapAsAMove = true;
+}
 def BUNDLE : StandardPseudoInstruction {
   let OutOperandList = (outs);
   let InOperandList = (ins variable_ops);

llvm/lib/CodeGen/MIRParser/MIParser.cpp

@@ -2876,14 +2876,14 @@ bool MIParser::parseLaneMaskOperand(MachineOperand &Dest) {
 
   lex();
   if (expectAndConsume(MIToken::lparen))
-    return error("expected syntax lanemask(...)");
+    return error("lanemask should begin with '('.");
 
   LaneBitmask LaneMask = LaneBitmask::getAll();
   // Parse lanemask.
   if (Token.isNot(MIToken::IntegerLiteral) && Token.isNot(MIToken::HexLiteral))
-    return error("expected a lane mask");
+    return error("expected a valid lane mask value.");
   static_assert(sizeof(LaneBitmask::Type) == sizeof(uint64_t),
-                "Use correct get-function for lane mask");
+                "Use correct get-function for lane mask.");
   LaneBitmask::Type V;
   if (getUint64(V))
     return error("invalid lanemask value");

llvm/lib/CodeGen/MachineVerifier.cpp

@@ -2414,6 +2414,34 @@ void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
     }
     break;
   }
+  case TargetOpcode::COPY_LANEMASK: {
+    const MachineOperand &DstOp = MI->getOperand(0);
+    const MachineOperand &SrcOp = MI->getOperand(1);
+    const MachineOperand &LaneMaskOp = MI->getOperand(2);
+    const Register SrcReg = SrcOp.getReg();
+    const Register DstReg = DstOp.getReg();
+    const LaneBitmask LaneMask = LaneMaskOp.getLaneMask();
+
+    if (!SrcReg.isPhysical() || !DstReg.isPhysical()) {
+      if (!SrcReg.isPhysical()) {
+        report("Copy with lanemask Instruction uses virtual register", &SrcOp,
+               1);
+      }
+      if (!DstReg.isPhysical()) {
+        report("Copy with lanemask Instruction uses virtual register", &DstOp,
+               0);
+      }
+      break;
+    }
+
+    if (LaneMask.none())
+      report("Lanemask takes up the zero value", MI);
+
+    if (LaneMask.all())
+      report("Copy Instruction can be used instead of copy with lanemask", MI);
+
+    break;
+  }
   case TargetOpcode::STATEPOINT: {
     StatepointOpers SO(MI);
     if (!MI->getOperand(SO.getIDPos()).isImm() ||

llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-0.mir

@@ -0,0 +1,13 @@
+# RUN: not llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -verify-machineinstrs %s -o /dev/null 2>&1 | FileCheck %s
+
+---
+name: test_missing_rparen
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $vgpr0
+
+    ; CHECK: [[@LINE+1]]:47: lanemask should be terminated by ')'. 
+    $vgpr1 = COPY_LANEMASK $vgpr0, lanemask(16
+    S_ENDPGM 0
+...

llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-1.mir

@@ -0,0 +1,13 @@
+# RUN: not llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -verify-machineinstrs %s -o /dev/null 2>&1 | FileCheck %s
+
+---
+name: test_missing_lparen
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $vgpr0
+
+    ; CHECK: [[@LINE+1]]:45: lanemask should begin with '('. 
+    $vgpr1 = COPY_LANEMASK $vgpr0, lanemask 14)
+    S_ENDPGM 0
+...

llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-2.mir

@@ -0,0 +1,13 @@
+# RUN: not llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -verify-machineinstrs %s -o /dev/null 2>&1 | FileCheck %s
+
+---
+name: test_wrong_lanemask_type
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $vgpr0
+
+    ; CHECK: [[@LINE+1]]:45: expected a valid lane mask value. 
+    $vgpr1 = COPY_LANEMASK $vgpr0, lanemask(undef)
+    S_ENDPGM 0
+...

llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand.mir

@@ -0,0 +1,17 @@
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -verify-machineinstrs -o - %s | FileCheck %s
+
+# This test checks for the correctness of the MIR parser for lanemask
+
+# CHECK-LABEL: name: test_lanemask_operand
+# CHECK: COPY_LANEMASK $vgpr0, lanemask(0x0000000000000020)
+---
+name: test_lanemask_operand
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $vgpr0
+
+    $vgpr1 = COPY_LANEMASK $vgpr0, lanemask(32)
+    S_ENDPGM 0
+...
+

llvm/test/MachineVerifier/verifier-copyLanemask0.mir

@@ -0,0 +1,14 @@
+# RUN: not --crash llc -o - -mtriple=amdgcn-amd-amdhsa -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# REQUIRES: amdgpu-registered-target
+
+---
+name: test_copy_lanemask_instruction_0
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $vgpr0, $vgpr1
+
+    $vgpr2 = COPY_LANEMASK $vgpr0, lanemask(0)
+    $vgpr3 = COPY_LANEMASK $vgpr1, lanemask(0xFFFFFFFFFFFFFFFF)
+    S_ENDPGM 0
+...