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[RISCV] add load/store misched/PostRA cluster options
Some processors benefit more from store clustering than load clustering, and vice-versa, depending on factors that are exclusive to each one (e.g. macrofusions implemented). Likewise, certain optimizations benefits more from misched clustering than postRA clustering. Macrofusions are again an example: in a processor with store pair macrofusions, like the veyron-v1, it is observed that misched clustering increases the amount of macrofusions more than postRA clustering. This of course isn't necessarily true for other processors, but it shows that processors can benefit from a more fine grained control of clustering mutations, and each one is able to do it differently. Add 4 new clustering options to be used with the existing riscv-misched-load-store-clustering and riscv-postmisched-load-store-clustering: - riscv-misched-load-clustering and riscv-misched-store-clustering: enable/disable load/store clustering during misched; - riscv-postmisched-load-clustering and riscv-postmisched-store-clustering: enable/disable load/store clustering during PostRA. To preserve the existing behavior of the existing flags all options added are default 'true'. Note that the two existing flags have precedence, so setting "riscv-misched-load-store-clustering=false" will disable load mutations even if setting riscv-misched-load-clustering=true. Same thing with stores and with the postRA options. For the veyron-v1 case mentioned above, to enable just the store clustering during misched, offline everything else: -mllvm -riscv-misched-load-clustering=false -mllvm -riscv-postmisched-load-store-clustering=false
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llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

Lines changed: 34 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -99,11 +99,31 @@ static cl::opt<bool> EnableMISchedLoadStoreClustering(
9999
cl::desc("Enable load and store clustering in the machine scheduler"),
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cl::init(true));
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102+
static cl::opt<bool> EnableMISchedLoadClustering(
103+
"riscv-misched-load-clustering", cl::Hidden,
104+
cl::desc("Enable load clustering in the machine scheduler"),
105+
cl::init(true));
106+
107+
static cl::opt<bool> EnableMISchedStoreClustering(
108+
"riscv-misched-store-clustering", cl::Hidden,
109+
cl::desc("Enable store clustering in the machine scheduler"),
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cl::init(true));
111+
102112
static cl::opt<bool> EnablePostMISchedLoadStoreClustering(
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"riscv-postmisched-load-store-clustering", cl::Hidden,
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cl::desc("Enable PostRA load and store clustering in the machine scheduler"),
105115
cl::init(true));
106116

117+
static cl::opt<bool> EnablePostMISchedLoadClustering(
118+
"riscv-postmisched-load-clustering", cl::Hidden,
119+
cl::desc("Enable PostRA load clustering in the machine scheduler"),
120+
cl::init(true));
121+
122+
static cl::opt<bool> EnablePostMISchedStoreClustering(
123+
"riscv-postmisched-store-clustering", cl::Hidden,
124+
cl::desc("Enable PostRA store clustering in the machine scheduler"),
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cl::init(true));
126+
107127
static cl::opt<bool>
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EnableVLOptimizer("riscv-enable-vl-optimizer",
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cl::desc("Enable the RISC-V VL Optimizer pass"),
@@ -301,10 +321,13 @@ ScheduleDAGInstrs *
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RISCVTargetMachine::createMachineScheduler(MachineSchedContext *C) const {
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ScheduleDAGMILive *DAG = createSchedLive(C);
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if (EnableMISchedLoadStoreClustering) {
304-
DAG->addMutation(createLoadClusterDAGMutation(
305-
DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true));
306-
DAG->addMutation(createStoreClusterDAGMutation(
307-
DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true));
324+
if (EnableMISchedLoadClustering)
325+
DAG->addMutation(createLoadClusterDAGMutation(
326+
DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true));
327+
328+
if (EnableMISchedStoreClustering)
329+
DAG->addMutation(createStoreClusterDAGMutation(
330+
DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true));
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}
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310333
const RISCVSubtarget &ST = C->MF->getSubtarget<RISCVSubtarget>();
@@ -318,10 +341,13 @@ ScheduleDAGInstrs *
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RISCVTargetMachine::createPostMachineScheduler(MachineSchedContext *C) const {
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ScheduleDAGMI *DAG = createSchedPostRA(C);
320343
if (EnablePostMISchedLoadStoreClustering) {
321-
DAG->addMutation(createLoadClusterDAGMutation(
322-
DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true));
323-
DAG->addMutation(createStoreClusterDAGMutation(
324-
DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true));
344+
if (EnablePostMISchedLoadClustering)
345+
DAG->addMutation(createLoadClusterDAGMutation(
346+
DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true));
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348+
if (EnablePostMISchedStoreClustering)
349+
DAG->addMutation(createStoreClusterDAGMutation(
350+
DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true));
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}
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327353
return DAG;

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