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[Mips] Fix atomic min/max generate mips4 instructions when compiling for mips2
Fix #145411.
1 parent 5d8e8e8 commit 1792b48

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2 files changed

+709
-25
lines changed

2 files changed

+709
-25
lines changed

‎llvm/lib/Target/Mips/MipsExpandPseudo.cpp

Lines changed: 188 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -433,23 +433,44 @@ bool MipsExpandPseudo::expandAtomicBinOpSubword(
433433
Register OldVal = I->getOperand(6).getReg();
434434
Register BinOpRes = I->getOperand(7).getReg();
435435
Register StoreVal = I->getOperand(8).getReg();
436+
bool NoMovnInstr = (IsMin || IsMax) && !STI->hasMips4() && !STI->hasMips32();
436437

437438
const BasicBlock *LLVM_BB = BB.getBasicBlock();
438439
MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
440+
MachineBasicBlock *loop1MBB;
441+
MachineBasicBlock *loop2MBB;
442+
if (NoMovnInstr) {
443+
loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
444+
loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
445+
}
439446
MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
440447
MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
441448
MachineFunction::iterator It = ++BB.getIterator();
442449
MF->insert(It, loopMBB);
450+
if (NoMovnInstr) {
451+
MF->insert(It, loop1MBB);
452+
MF->insert(It, loop2MBB);
453+
}
443454
MF->insert(It, sinkMBB);
444455
MF->insert(It, exitMBB);
445456

446457
exitMBB->splice(exitMBB->begin(), &BB, std::next(I), BB.end());
447458
exitMBB->transferSuccessorsAndUpdatePHIs(&BB);
448459

449460
BB.addSuccessor(loopMBB, BranchProbability::getOne());
450-
loopMBB->addSuccessor(sinkMBB);
451-
loopMBB->addSuccessor(loopMBB);
461+
if (NoMovnInstr) {
462+
loopMBB->addSuccessor(loop1MBB);
463+
loopMBB->addSuccessor(loop2MBB);
464+
} else {
465+
loopMBB->addSuccessor(sinkMBB);
466+
loopMBB->addSuccessor(loopMBB);
467+
}
452468
loopMBB->normalizeSuccProbs();
469+
if (NoMovnInstr) {
470+
loop1MBB->addSuccessor(loop2MBB);
471+
loop2MBB->addSuccessor(loopMBB);
472+
loop2MBB->addSuccessor(exitMBB, BranchProbability::getOne());
473+
}
453474

454475
BuildMI(loopMBB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
455476
if (IsNand) {
@@ -526,7 +547,7 @@ bool MipsExpandPseudo::expandAtomicBinOpSubword(
526547
BuildMI(loopMBB, DL, TII->get(OR), BinOpRes)
527548
.addReg(BinOpRes)
528549
.addReg(Scratch4);
529-
} else {
550+
} else if (STI->hasMips4() || STI->hasMips32()) {
530551
// max: move BinOpRes, StoreVal
531552
// movn BinOpRes, Incr, Scratch4, BinOpRes
532553
// min: move BinOpRes, StoreVal
@@ -538,12 +559,59 @@ bool MipsExpandPseudo::expandAtomicBinOpSubword(
538559
.addReg(Incr)
539560
.addReg(Scratch4)
540561
.addReg(BinOpRes);
562+
} else {
563+
// if min:
564+
// loopMBB: move BinOpRes, StoreVal
565+
// beq Scratch4, 0, loop1MBB
566+
// j loop2MBB
567+
// loop1MBB: move BinOpRes, Incr
568+
// loop2MBB: and BinOpRes, BinOpRes, Mask
569+
// and StoreVal, OlddVal, Mask2
570+
// or StoreVal, StoreVal, BinOpRes
571+
// StoreVal<tied1> = sc StoreVal, 0(Ptr)
572+
// beq StoreVal, zero, loopMBB
573+
//
574+
// if max:
575+
// loopMBB: move BinOpRes, Incr
576+
// beq Scratch4, 0, loop1MBB
577+
// j loop2MBB
578+
// loop1MBB: move BinOpRes, StoreVal
579+
// loop2MBB: and BinOpRes, BinOpRes, Mask
580+
// and StoreVal, OlddVal, Mask2
581+
// or StoreVal, StoreVal, BinOpRes
582+
// StoreVal<tied1> = sc StoreVal, 0(Ptr)
583+
// beq StoreVal, zero, loopMBB
584+
if (IsMin) {
585+
BuildMI(loopMBB, DL, TII->get(OR), BinOpRes)
586+
.addReg(StoreVal)
587+
.addReg(Mips::ZERO);
588+
BuildMI(loop1MBB, DL, TII->get(OR), BinOpRes)
589+
.addReg(Incr)
590+
.addReg(Mips::ZERO);
591+
} else {
592+
BuildMI(loopMBB, DL, TII->get(OR), BinOpRes)
593+
.addReg(Incr)
594+
.addReg(Mips::ZERO);
595+
BuildMI(loop1MBB, DL, TII->get(OR), BinOpRes)
596+
.addReg(StoreVal)
597+
.addReg(Mips::ZERO);
598+
}
599+
BuildMI(loopMBB, DL, TII->get(BEQ))
600+
.addReg(Scratch4)
601+
.addReg(Mips::ZERO)
602+
.addMBB(loop1MBB);
603+
BuildMI(loopMBB, DL, TII->get(Mips::J)).addMBB(loop2MBB);
541604
}
542605

543606
// and BinOpRes, BinOpRes, Mask
544-
BuildMI(loopMBB, DL, TII->get(Mips::AND), BinOpRes)
545-
.addReg(BinOpRes)
546-
.addReg(Mask);
607+
if (NoMovnInstr)
608+
BuildMI(loop2MBB, DL, TII->get(Mips::AND), BinOpRes)
609+
.addReg(BinOpRes)
610+
.addReg(Mask);
611+
else
612+
BuildMI(loopMBB, DL, TII->get(Mips::AND), BinOpRes)
613+
.addReg(BinOpRes)
614+
.addReg(Mask);
547615

548616
} else if (!IsSwap) {
549617
// <binop> binopres, oldval, incr2
@@ -565,14 +633,37 @@ bool MipsExpandPseudo::expandAtomicBinOpSubword(
565633
// or StoreVal, StoreVal, BinOpRes
566634
// StoreVal<tied1> = sc StoreVal, 0(Ptr)
567635
// beq StoreVal, zero, loopMBB
568-
BuildMI(loopMBB, DL, TII->get(Mips::AND), StoreVal)
569-
.addReg(OldVal).addReg(Mask2);
570-
BuildMI(loopMBB, DL, TII->get(Mips::OR), StoreVal)
571-
.addReg(StoreVal).addReg(BinOpRes);
572-
BuildMI(loopMBB, DL, TII->get(SC), StoreVal)
573-
.addReg(StoreVal).addReg(Ptr).addImm(0);
574-
BuildMI(loopMBB, DL, TII->get(BEQ))
575-
.addReg(StoreVal).addReg(Mips::ZERO).addMBB(loopMBB);
636+
if (NoMovnInstr) {
637+
BuildMI(loop2MBB, DL, TII->get(Mips::AND), StoreVal)
638+
.addReg(OldVal)
639+
.addReg(Mask2);
640+
BuildMI(loop2MBB, DL, TII->get(Mips::OR), StoreVal)
641+
.addReg(StoreVal)
642+
.addReg(BinOpRes);
643+
BuildMI(loop2MBB, DL, TII->get(SC), StoreVal)
644+
.addReg(StoreVal)
645+
.addReg(Ptr)
646+
.addImm(0);
647+
BuildMI(loop2MBB, DL, TII->get(BEQ))
648+
.addReg(StoreVal)
649+
.addReg(Mips::ZERO)
650+
.addMBB(loopMBB);
651+
} else {
652+
BuildMI(loopMBB, DL, TII->get(Mips::AND), StoreVal)
653+
.addReg(OldVal)
654+
.addReg(Mask2);
655+
BuildMI(loopMBB, DL, TII->get(Mips::OR), StoreVal)
656+
.addReg(StoreVal)
657+
.addReg(BinOpRes);
658+
BuildMI(loopMBB, DL, TII->get(SC), StoreVal)
659+
.addReg(StoreVal)
660+
.addReg(Ptr)
661+
.addImm(0);
662+
BuildMI(loopMBB, DL, TII->get(BEQ))
663+
.addReg(StoreVal)
664+
.addReg(Mips::ZERO)
665+
.addMBB(loopMBB);
666+
}
576667

577668
// sinkMBB:
578669
// and maskedoldval1,oldval,mask
@@ -601,6 +692,10 @@ bool MipsExpandPseudo::expandAtomicBinOpSubword(
601692

602693
LivePhysRegs LiveRegs;
603694
computeAndAddLiveIns(LiveRegs, *loopMBB);
695+
if (NoMovnInstr) {
696+
computeAndAddLiveIns(LiveRegs, *loop1MBB);
697+
computeAndAddLiveIns(LiveRegs, *loop2MBB);
698+
}
604699
computeAndAddLiveIns(LiveRegs, *sinkMBB);
605700
computeAndAddLiveIns(LiveRegs, *exitMBB);
606701

@@ -747,20 +842,41 @@ bool MipsExpandPseudo::expandAtomicBinOp(MachineBasicBlock &BB,
747842
llvm_unreachable("Unknown pseudo atomic!");
748843
}
749844

845+
bool NoMovnInstr = (IsMin || IsMax) && !STI->hasMips4() && !STI->hasMips32();
750846
const BasicBlock *LLVM_BB = BB.getBasicBlock();
751847
MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
848+
MachineBasicBlock *loop1MBB;
849+
MachineBasicBlock *loop2MBB;
850+
if (NoMovnInstr) {
851+
loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
852+
loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
853+
}
752854
MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
753855
MachineFunction::iterator It = ++BB.getIterator();
754856
MF->insert(It, loopMBB);
857+
if (NoMovnInstr) {
858+
MF->insert(It, loop1MBB);
859+
MF->insert(It, loop2MBB);
860+
}
755861
MF->insert(It, exitMBB);
756862

757863
exitMBB->splice(exitMBB->begin(), &BB, std::next(I), BB.end());
758864
exitMBB->transferSuccessorsAndUpdatePHIs(&BB);
759865

760866
BB.addSuccessor(loopMBB, BranchProbability::getOne());
761-
loopMBB->addSuccessor(exitMBB);
762-
loopMBB->addSuccessor(loopMBB);
867+
if (NoMovnInstr) {
868+
loopMBB->addSuccessor(loop1MBB);
869+
loopMBB->addSuccessor(loop2MBB);
870+
} else {
871+
loopMBB->addSuccessor(exitMBB);
872+
loopMBB->addSuccessor(loopMBB);
873+
}
763874
loopMBB->normalizeSuccProbs();
875+
if (NoMovnInstr) {
876+
loop1MBB->addSuccessor(loop2MBB);
877+
loop2MBB->addSuccessor(loopMBB);
878+
loop2MBB->addSuccessor(exitMBB, BranchProbability::getOne());
879+
}
764880

765881
BuildMI(loopMBB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
766882
assert((OldVal != Ptr) && "Clobbered the wrong ptr reg!");
@@ -803,7 +919,7 @@ bool MipsExpandPseudo::expandAtomicBinOp(MachineBasicBlock &BB,
803919
BuildMI(loopMBB, DL, TII->get(OR), Scratch)
804920
.addReg(Scratch)
805921
.addReg(Scratch2);
806-
} else {
922+
} else if (STI->hasMips4() || STI->hasMips32()) {
807923
// max: move Scratch, OldVal
808924
// movn Scratch, Incr, Scratch2, Scratch
809925
// min: move Scratch, OldVal
@@ -815,6 +931,38 @@ bool MipsExpandPseudo::expandAtomicBinOp(MachineBasicBlock &BB,
815931
.addReg(Incr)
816932
.addReg(Scratch2)
817933
.addReg(Scratch);
934+
} else {
935+
// if min:
936+
// loopMBB: move Scratch, OldVal
937+
// beq Scratch2_32, 0, loop1MBB
938+
// j loop2MBB
939+
// loop1MBB: move Scratch, Incr
940+
// loop2MBB: sc $2, 0($4)
941+
// beqz $2, $BB0_1
942+
// nop
943+
//
944+
// if max:
945+
// loopMBB: move Scratch, Incr
946+
// beq Scratch2_32, 0, loop1MBB
947+
// j loop2MBB
948+
// loop1MBB: move Scratch, OldVal
949+
// loop2MBB: sc $2, 0($4)
950+
// beqz $2, $BB0_1
951+
// nop
952+
if (IsMin) {
953+
BuildMI(loopMBB, DL, TII->get(OR), Scratch).addReg(OldVal).addReg(ZERO);
954+
BuildMI(loop1MBB, DL, TII->get(OR), Scratch).addReg(Incr).addReg(ZERO);
955+
} else {
956+
BuildMI(loopMBB, DL, TII->get(OR), Scratch).addReg(Incr).addReg(ZERO);
957+
BuildMI(loop1MBB, DL, TII->get(OR), Scratch)
958+
.addReg(OldVal)
959+
.addReg(ZERO);
960+
}
961+
BuildMI(loopMBB, DL, TII->get(BEQ))
962+
.addReg(Scratch2_32)
963+
.addReg(ZERO)
964+
.addMBB(loop1MBB);
965+
BuildMI(loopMBB, DL, TII->get(Mips::J)).addMBB(loop2MBB);
818966
}
819967

820968
} else if (Opcode) {
@@ -830,20 +978,35 @@ bool MipsExpandPseudo::expandAtomicBinOp(MachineBasicBlock &BB,
830978
BuildMI(loopMBB, DL, TII->get(OR), Scratch).addReg(Incr).addReg(ZERO);
831979
}
832980

833-
BuildMI(loopMBB, DL, TII->get(SC), Scratch)
834-
.addReg(Scratch)
835-
.addReg(Ptr)
836-
.addImm(0);
837-
BuildMI(loopMBB, DL, TII->get(BEQ))
838-
.addReg(Scratch)
839-
.addReg(ZERO)
840-
.addMBB(loopMBB);
981+
if (NoMovnInstr) {
982+
BuildMI(loop2MBB, DL, TII->get(SC), Scratch)
983+
.addReg(Scratch)
984+
.addReg(Ptr)
985+
.addImm(0);
986+
BuildMI(loop2MBB, DL, TII->get(BEQ))
987+
.addReg(Scratch)
988+
.addReg(ZERO)
989+
.addMBB(loopMBB);
990+
} else {
991+
BuildMI(loopMBB, DL, TII->get(SC), Scratch)
992+
.addReg(Scratch)
993+
.addReg(Ptr)
994+
.addImm(0);
995+
BuildMI(loopMBB, DL, TII->get(BEQ))
996+
.addReg(Scratch)
997+
.addReg(ZERO)
998+
.addMBB(loopMBB);
999+
}
8411000

8421001
NMBBI = BB.end();
8431002
I->eraseFromParent();
8441003

8451004
LivePhysRegs LiveRegs;
8461005
computeAndAddLiveIns(LiveRegs, *loopMBB);
1006+
if (!STI->hasMips4() && !STI->hasMips32()) {
1007+
computeAndAddLiveIns(LiveRegs, *loop1MBB);
1008+
computeAndAddLiveIns(LiveRegs, *loop2MBB);
1009+
}
8471010
computeAndAddLiveIns(LiveRegs, *exitMBB);
8481011

8491012
return true;

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