|
| 1 | +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 |
| 2 | + |
| 3 | +; RUN: opt -passes=instsimplify -S < %s | FileCheck %s |
| 4 | + |
| 5 | +; Test that intrinsics wasm call are constant folded |
| 6 | + |
| 7 | +; all_non_zero: a splat that is all non_zero |
| 8 | +; not_all_non_zero: a splat that is all one, except for 0 in the first location |
| 9 | + |
| 10 | +; all_zero: a splat that is all zero |
| 11 | +; not_all_zero: a splat that is all zero, except for a non-zero in the first location |
| 12 | + |
| 13 | +target triple = "wasm32-unknown-unknown" |
| 14 | + |
| 15 | +define void @all_true_splat_not_all_non_zero(ptr %ptr) { |
| 16 | +; CHECK-LABEL: define void @all_true_splat_not_all_non_zero( |
| 17 | +; CHECK-SAME: ptr [[PTR:%.*]]) { |
| 18 | +; CHECK-NEXT: store volatile i32 0, ptr [[PTR]], align 4 |
| 19 | +; CHECK-NEXT: store volatile i32 0, ptr [[PTR]], align 4 |
| 20 | +; CHECK-NEXT: store volatile i32 0, ptr [[PTR]], align 4 |
| 21 | +; CHECK-NEXT: store volatile i32 0, ptr [[PTR]], align 4 |
| 22 | +; CHECK-NEXT: store volatile i32 0, ptr [[PTR]], align 4 |
| 23 | +; CHECK-NEXT: ret void |
| 24 | +; |
| 25 | + %a = call i32 @llvm.wasm.alltrue(<16 x i8> <i8 0, i8 1, i8 2, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>) |
| 26 | + store volatile i32 %a, ptr %ptr |
| 27 | + |
| 28 | + %b = call i32 @llvm.wasm.alltrue(<8 x i16> <i16 0, i16 1, i16 2, i16 1, i16 1, i16 1, i16 1, i16 1>) |
| 29 | + store volatile i32 %b, ptr %ptr |
| 30 | + |
| 31 | + %c = call i32 @llvm.wasm.alltrue(<4 x i32> <i32 0, i32 1, i32 1, i32 1>) |
| 32 | + store volatile i32 %c, ptr %ptr |
| 33 | + |
| 34 | + %d = call i32 @llvm.wasm.alltrue(<2 x i64> <i64 0, i64 42>) |
| 35 | + store volatile i32 %d, ptr %ptr |
| 36 | + |
| 37 | + %e = call i32 @llvm.wasm.alltrue(<4 x i64> <i64 0, i64 1, i64 1, i64 1>) |
| 38 | + store volatile i32 %e, ptr %ptr |
| 39 | + |
| 40 | + ret void |
| 41 | +} |
| 42 | + |
| 43 | +define void @all_true_splat_all_non_zero(ptr %ptr) { |
| 44 | +; CHECK-LABEL: define void @all_true_splat_all_non_zero( |
| 45 | +; CHECK-SAME: ptr [[PTR:%.*]]) { |
| 46 | +; CHECK-NEXT: store volatile i32 1, ptr [[PTR]], align 4 |
| 47 | +; CHECK-NEXT: store volatile i32 1, ptr [[PTR]], align 4 |
| 48 | +; CHECK-NEXT: store volatile i32 1, ptr [[PTR]], align 4 |
| 49 | +; CHECK-NEXT: store volatile i32 1, ptr [[PTR]], align 4 |
| 50 | +; CHECK-NEXT: store volatile i32 1, ptr [[PTR]], align 4 |
| 51 | +; CHECK-NEXT: ret void |
| 52 | +; |
| 53 | + %a = call i32 @llvm.wasm.alltrue(<16 x i8> <i8 1, i8 3, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>) |
| 54 | + store volatile i32 %a, ptr %ptr |
| 55 | + |
| 56 | + %b = call i32 @llvm.wasm.alltrue(<8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>) |
| 57 | + store volatile i32 %b, ptr %ptr |
| 58 | + |
| 59 | + %c = call i32 @llvm.wasm.alltrue(<4 x i32> <i32 1, i32 1, i32 1, i32 1>) |
| 60 | + store volatile i32 %c, ptr %ptr |
| 61 | + |
| 62 | + %d = call i32 @llvm.wasm.alltrue(<2 x i64> <i64 2, i64 2>) |
| 63 | + store volatile i32 %d, ptr %ptr |
| 64 | + |
| 65 | + %e = call i32 @llvm.wasm.alltrue(<4 x i64> <i64 1, i64 2, i64 1, i64 1>) |
| 66 | + store volatile i32 %e, ptr %ptr |
| 67 | + |
| 68 | + ret void |
| 69 | +} |
| 70 | + |
| 71 | + |
| 72 | +define void @any_true_splat_all_zero(ptr %ptr) { |
| 73 | +; CHECK-LABEL: define void @any_true_splat_all_zero( |
| 74 | +; CHECK-SAME: ptr [[PTR:%.*]]) { |
| 75 | +; CHECK-NEXT: store volatile i32 0, ptr [[PTR]], align 4 |
| 76 | +; CHECK-NEXT: store volatile i32 0, ptr [[PTR]], align 4 |
| 77 | +; CHECK-NEXT: store volatile i32 0, ptr [[PTR]], align 4 |
| 78 | +; CHECK-NEXT: store volatile i32 0, ptr [[PTR]], align 4 |
| 79 | +; CHECK-NEXT: store volatile i32 0, ptr [[PTR]], align 4 |
| 80 | +; CHECK-NEXT: ret void |
| 81 | +; |
| 82 | + %a = call i32 @llvm.wasm.anytrue(<16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>) |
| 83 | + store volatile i32 %a, ptr %ptr |
| 84 | + |
| 85 | + %b = call i32 @llvm.wasm.anytrue(<8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>) |
| 86 | + store volatile i32 %b, ptr %ptr |
| 87 | + |
| 88 | + %c = call i32 @llvm.wasm.anytrue(<4 x i32> <i32 0, i32 0, i32 0, i32 0>) |
| 89 | + store volatile i32 %c, ptr %ptr |
| 90 | + |
| 91 | + %d = call i32 @llvm.wasm.anytrue(<2 x i64> <i64 0, i64 0>) |
| 92 | + store volatile i32 %d, ptr %ptr |
| 93 | + |
| 94 | + %e = call i32 @llvm.wasm.anytrue(<4 x i64> <i64 0, i64 0, i64 0, i64 0>) |
| 95 | + store volatile i32 %e, ptr %ptr |
| 96 | + |
| 97 | + ret void |
| 98 | +} |
| 99 | + |
| 100 | + |
| 101 | +define void @any_true_splat_not_all_zero(ptr %ptr) { |
| 102 | +; CHECK-LABEL: define void @any_true_splat_not_all_zero( |
| 103 | +; CHECK-SAME: ptr [[PTR:%.*]]) { |
| 104 | +; CHECK-NEXT: store volatile i32 1, ptr [[PTR]], align 4 |
| 105 | +; CHECK-NEXT: store volatile i32 1, ptr [[PTR]], align 4 |
| 106 | +; CHECK-NEXT: store volatile i32 1, ptr [[PTR]], align 4 |
| 107 | +; CHECK-NEXT: store volatile i32 1, ptr [[PTR]], align 4 |
| 108 | +; CHECK-NEXT: store volatile i32 1, ptr [[PTR]], align 4 |
| 109 | +; CHECK-NEXT: ret void |
| 110 | +; |
| 111 | + %a = call i32 @llvm.wasm.anytrue(<16 x i8> <i8 1, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>) |
| 112 | + store volatile i32 %a, ptr %ptr |
| 113 | + |
| 114 | + %b = call i32 @llvm.wasm.anytrue(<8 x i16> <i16 3, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>) |
| 115 | + store volatile i32 %b, ptr %ptr |
| 116 | + |
| 117 | + %c = call i32 @llvm.wasm.anytrue(<4 x i32> <i32 1, i32 0, i32 0, i32 0>) |
| 118 | + store volatile i32 %c, ptr %ptr |
| 119 | + |
| 120 | + %d = call i32 @llvm.wasm.anytrue(<2 x i64> <i64 -1, i64 0>) |
| 121 | + store volatile i32 %d, ptr %ptr |
| 122 | + |
| 123 | + %e = call i32 @llvm.wasm.anytrue(<4 x i64> <i64 2, i64 0, i64 0, i64 0>) |
| 124 | + store volatile i32 %e, ptr %ptr |
| 125 | + |
| 126 | + ret void |
| 127 | +} |
0 commit comments